Parallel Data Scrambling and Balance Coding for Low-Noise DRAM I/O
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Solution Overview
Problem
Conventional methods for reducing noise in semiconductor devices, such as DRAM, using single-ended parallel interfaces face limitations as they either require additional pins or do not effectively address switching noise, with existing DC balance coding failing to minimize noise caused by temporal changes in input bit values.
Innovation Solution
A method and system that incorporates a scrambler to rearrange the order of bits in parallel data and a balance coding block to generate a balance code, ensuring a controlled difference between logic levels, thereby reducing noise due to parasitic inductance and switching noise through a single-ended parallel interface.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If differential signaling is used to reduce noise, then noise is reduced, but the number of pins required increases
Solution Approach 1:
The patent changes the parameters of single-ended signaling by applying scrambling codes and DC balance coding to the data stream. This transforms the signal characteristics to reduce noise effects without changing the fundamental single-ended transmission mode, thereby avoiding the need for additional pins while still achieving noise reduction
2Object-affected harmful factors
If conventional DC balance coding is used to reduce noise, then DC noise is reduced, but switching noise caused by temporal changes in input bit values is not effectively addressed
Solution Approach 1:
The patent applies scrambling codes to the data stream before transmission. This preliminary action randomizes the bit pattern in advance, preventing large numbers of bits from changing simultaneously at any point in time, thereby proactively reducing switching noise before it can affect the signal integrity
Solution Approach 2:
The patent combines DC balance coding with scrambling codes, changing the temporal distribution parameters of bit transitions. This dual approach controls both the DC component and the switching dynamics, effectively addressing both DC noise and switching noise that conventional DC balance coding alone cannot handle
3Productivity
If more bits are transmitted in parallel to increase data rate, then transmission rate is improved, but noise due to parasitic inductance increases
Solution Approach 1:
The patent applies scrambling codes and DC balance coding to control the temporal distribution of bit transitions in parallel data streams. This changes the statistical parameters of current variations, reducing the cumulative noise effect from parasitic inductance while maintaining high parallel transmission rates
Data Source
AI summary
Semiconductor devices, a system including said semiconductor devices and methods thereof are provided. An example semiconductor device may receive data scheduled for transmission, scramble an order of bits within the received data, the scrambled order arranged in accordance with a given pseudo-random sequence. The received data may be balanced such that a difference between a first number of the bits within the received data equal to a first logic level and a second number of bits within the received data equal to a second logic level is below a threshold. The balanced and scrambled received data may then be transmitted. The example semiconductor device may perform the scrambling and balancing operations in any order. Likewise, on a receiving end, another semiconductor device may decode the original data by unscrambling and unbalancing the transmitted data. The unscrambling and unbalancing operations may be performed in an order based upon the order in which the transmitted data is scrambled and balanced.