Parallel Data Transmission With Bit Inversion to Cut Switching Noise
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Solution Overview
Problem
Existing data transmission systems face challenges in efficiently using RAM, suppressing noise, and reducing power consumption, particularly in high-speed communication ICs, where the increasing bit width of parallel signals leads to increased synchronous operations and noise, and existing methods struggle when applied to FPGA devices with ECC circuits.
Innovation Solution
A data transmission system that generates a 1-bit inversion instruction signal to determine if the number of changed bits in 64-bit data exceeds a threshold, inverts the data polarity accordingly, and adds a 7-bit error correcting code, allowing for efficient transmission and reception while reducing synchronous operations and noise.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the signal speed is increased to 40 Gbps or 100 Gbps, then the communication capacity is improved, but the bit width of parallel signal increases requiring more FFs which increases switching noise and power consumption
Solution Approach 1:
The patent applies inversion by detecting when the number of changed bits exceeds a threshold and inverting the polarity of the parallel signal. This reduces the number of synchronous operations of FFs by half, thereby reducing switching noise generated by simultaneous signal changes across multiple bits during high-speed data transmission
2Speed
If the signal speed is increased to 40 Gbps or 100 Gbps, then the communication capacity is improved, but the bit width of parallel signal increases requiring more FFs which increases power consumption
Solution Approach 1:
The patent reduces power consumption by inverting the parallel signal polarity when the number of changed bits exceeds a threshold. Since power consumption in CMOS-IC is proportional to the number of signal changes of FFs, this inversion technique reduces synchronous operations by half, thereby significantly reducing power consumption during high-speed communication
3Object-generated harmful factors
If a 1-bit inversion instruction signal is added to reduce synchronous operations, then switching noise and power consumption are reduced, but the total bit width becomes 73 bits which cannot be used in standard 72-bit width RAM
Solution Approach 1:
The patent achieves universality by integrating the inversion instruction signal into the existing 72-bit RAM structure. The 64-bit data bus already exists in the system, and the invention utilizes this existing infrastructure while adding only 1-bit inversion control, making the solution compatible with standard 72-bit RAM without requiring new memory architectures
4Object-generated harmful factors
If a 1-bit inversion instruction signal is added to reduce synchronous operations, then switching noise and power consumption are reduced, but the total bit width becomes 73 bits which deteriorates use efficiency of RAM
Solution Approach 1:
The patent maintains high RAM utilization efficiency by operating within the existing 72-bit width constraint. The system processes 64-bit data while using 1-bit inversion control that fits within the available 72-bit RAM capacity, avoiding waste of memory resources and maintaining efficient utilization of the storage medium
Data Source
AI summary
If the number of bits at which 64-bit width data has changed at the same time has exceeded a threshold, the data is outputted, with the polarity of each bit inverted. Otherwise, the data is outputted. A 7-bit width error correcting code is given to the outputted data and the inversion instruction signal indicating whether the number of the changed bits has exceeded the threshold. Error code correction is performed for the data and the inversion instruction signal with the use of the transmitted error correcting code. If the inversion instruction signal for which the error code correction has been performed indicates that the number of the changed bits has exceeded the threshold, the data for which the error code correction has been performed is outputted, with the polarity of each bit inverted. Otherwise, the data for which the error code correction has been performed is outputted.