Parallel Data Channel Clock Alignment Method

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Solution Overview

Problem

Existing methods for synchronizing data flows across multiple communication paths introduce unwanted jitter and narrow the valid data eye, making it challenging to maintain proper timing and alignment, especially at higher data rates.

Innovation Solution

The method involves selecting an optimal reference channel with minimal delay and aligning other channels to its center, thereby minimizing the addition of jitter and maintaining a wider valid data eye, while allowing for separate binary word alignment.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If delays are added to align data portions transmitted in parallel, then data synchronization is improved, but unwanted jitter is introduced and valid data eye is narrowed

Engineering Contradiction:
Improvedata synchronizationVSAvoidjitter and data eye narrowing
Core Design Contradiction:
ReliabilityVSObject-affected harmful factors

Solution Approach 1:

The patent segments the data alignment process into two independent stages: first aligning data-clock centers across all channels, then separately performing binary word alignment. This segmentation allows each stage to be optimized independently, reducing the cumulative jitter and data eye narrowing that would occur if a single unified alignment approach was used.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent performs preliminary data-clock alignment to establish a common reference time base across all channels before performing binary word alignment. This preliminary action creates a stable foundation that reduces the alignment adjustments needed during the second stage, thereby minimizing additional jitter and preserving data eye width.

Inventive Principle:
Principle #10Preliminary action

2Reliability

If delays are added to align data-clock centers, then data synchronization is improved, but valid data portion (data eye) is narrowed

Engineering Contradiction:
Improvedata synchronizationVSAvoidvalid data eye width
Core Design Contradiction:
ReliabilityVSManufacturing precision

Solution Approach 1:

By separating data-clock alignment from binary word alignment, the patent reduces the total delay required for synchronization. The data-clock alignment stage establishes temporal reference without requiring full word alignment, thereby minimizing the narrowing of valid data eye while still achieving proper synchronization.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent changes the alignment parameter from direct binary word alignment to data-clock center alignment first, then applies minimal additional adjustment for binary alignment. This parameter change approach allows synchronization to be achieved with smaller delay values, preserving data eye width while maintaining timing accuracy.

Inventive Principle:
Principle #35Parameter changes

3Reliability

If conventional alignment methods are used, then data synchronization is achieved, but interface ability to handle higher data rates is reduced

Engineering Contradiction:
Improvedata synchronizationVSAvoiddata rate handling capability
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The patent segments alignment into data-clock alignment followed by binary word alignment, which reduces the total delay overhead. This reduced delay allows the interface to maintain proper synchronization at higher data rates where timing is more critical and margin is more limited.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

By performing data-clock alignment as a preliminary step, the patent establishes a stable timing reference that reduces subsequent alignment requirements. This preliminary alignment action minimizes the cumulative delay and jitter, enabling the interface to operate reliably at higher data rates.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS8934592B2Method for reducing data alignment delays
Publication Date: 2015.01.13 ECI TELECOM LTD
  • US8934592B2 patent drawing
  • US8934592B2 patent drawing
  • US8934592B2 patent drawing

AI summary

A method is provided for synchronizing binary data transmitted in parallel via N channels. The method comprises performing at the receiver side, a data-clock-alignment for the data in the N channels by selecting an optimal reference channel to which no delay will be added, and adding an appropriate delay to each of the remaining channels, until their respective centers of valid data portions are aligned to each other, and associating clock edges with the centers of the valid data portions. The method is characterized in that the alignment is performed regardless to whether binary word alignment is simultaneously achieved or not, and wherein the optimal reference channel allows aligning the centers of valid data of all the channels while adding a minimal delay to a worst channel from among the remaining channels, wherein the worst channel carries valid data portions which are maximally shifted from those of the reference channel.