Parallel Data Comparators for Serial Stream Pattern Detection

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Solution Overview

Problem

Existing methods for searching a data sequence in a continuous serial bit stream are inefficient and require high-speed comparators, especially at high data rates, leading to increased complexity and the need for custom designs.

Innovation Solution

The method involves deserializing the input data stream into an N-bit wide bus and using N comparators to perform parallel comparisons, allowing each comparator to operate at a reduced rate, thereby reducing the overall operating frequency and enabling the use of off-the-shelf technology.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If a single high-speed comparator is used to search for data patterns in a serial bit stream at high data rates, then the search speed matches the bit rate, but the comparator requires custom high-speed design and increased complexity

Engineering Contradiction:
Improvesearch speedVSAvoidcomparator design complexity
Core Design Contradiction:
SpeedVSDevice complexity

Solution Approach 1:

The patent divides the single high-speed comparison task into multiple lower-speed comparators. Specifically, it uses multiple comparators operating in parallel, each handling a portion of the data width, thereby segmenting the high-speed operation into manageable lower-speed units that can be implemented with standard components

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent transitions from a single-dimensional high-speed time-based comparison to a multi-dimensional approach using multiple comparators operating in parallel. By adding the dimension of parallel processing with multiple comparators, the system achieves high effective search speed while each individual comparator operates at a reduced, manageable speed

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Ease of manufacture

If multiple comparators are used in parallel to reduce the operating frequency, then standard components can be used, but the timing and control system complexity increases

Engineering Contradiction:
Improvecomponent availabilityVSAvoidtiming and control complexity
Core Design Contradiction:
Ease of manufactureVSDevice complexity

Solution Approach 1:

The patent merges the outputs of multiple comparators and integrates their control signals into a unified timing and control structure. By combining the comparison results and synchronizing the parallel comparators under a coordinated control scheme, the system manages the complexity of multiple comparators while maintaining ease of manufacture through standard components

Inventive Principle:
Principle #5Merging (Combining)

3Device complexity

If traditional sequential comparison methods are used, then the system is simple to implement, but the search process takes a long period of time

Engineering Contradiction:
Improvesystem simplicityVSAvoidsearch time
Core Design Contradiction:
Device complexityVSLoss of time

Solution Approach 1:

The patent implements continuous parallel comparison across multiple comparators simultaneously processing different portions of the data stream. This eliminates the sequential waiting period inherent in traditional methods, as all comparators operate continuously and simultaneously, dramatically reducing search time while maintaining manageable system complexity

Inventive Principle:
Principle #20Continuity of useful action

Data Source

PatentUS7707234B2Use of multiple data comparators in parallel to trigger an oscilloscope on a pattern found in a serial data stream
Publication Date: 2010.04.27 TELEDYNE LECROY INC
  • US7707234B2 patent drawing
  • US7707234B2 patent drawing
  • US7707234B2 patent drawing

AI summary

A method and system are provided for determining a location of a predetermined N bit sequence in a data stream. The method comprises the steps of determining two N bit data words from consecutive bits of the data stream, and providing N, N bit comparators. A first N bits of the two N bit data words is compared with the predetermined N bit data sequence by a first of the N comparators, and a next N bits, starting at a second bit, of the two N bit data words are compared with the predetermined N bit sequence by a second of the N bit comparators. These comparisons are repeated, incrementing the starting bit, until N comparators have been employed and the first through N bits have been employed as the starting bit.