Parallel Data Compression Circuit for Multi-Type Transmission Latency
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Solution Overview
Problem
Existing data processing systems face latency issues when transmitting multiple types of data, such as image and distance data, due to the limitation of having only one compression path, which hinders efficient simultaneous transmission.
Innovation Solution
A data processing device with a data selector circuit that divides data into multiple types and employs multiple compression circuits for parallel compression and transmission, allowing for simultaneous compression and transmission of different data types.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a single compression path is used to compress data, then the device complexity is reduced, but the transmission latency increases when multiple types of data need to be transmitted simultaneously
Solution Approach 1:
The patent divides the compression system into multiple independent compression circuits (first compression circuit and second compression circuit), each handling different data types separately. This segmentation allows parallel processing of image data and other data types, reducing transmission latency while maintaining manageable device complexity through modular architecture
Solution Approach 2:
The patent transitions from a single-dimensional sequential compression path to a multi-dimensional parallel compression architecture. By adding the dimension of parallelism with multiple compression circuits operating simultaneously, the system reduces time latency without proportionally increasing overall system complexity
2Loss of time
If multiple compression circuits are used to compress multiple types of data in parallel, then the transmission latency is reduced, but the device complexity increases
Solution Approach 1:
The patent designs compression circuits that can handle different data types through standardized interfaces and control mechanisms. The first compression circuit handles image data while the second handles other data types, but both follow similar operational patterns, allowing the system to achieve parallel processing capability without proportionally increasing control complexity
Solution Approach 2:
The patent implements dynamic data type identification and routing mechanisms that adaptively direct different data types to appropriate compression circuits. This dynamic allocation optimizes parallel processing efficiency while managing device complexity through intelligent resource allocation rather than static rigid architecture
3Device complexity
If data is compressed sequentially through a single path, then the device structure is simplified, but the productivity of data transmission decreases
Solution Approach 1:
The patent segments the data transmission pipeline into parallel compression circuits, each dedicated to specific data types. This segmentation enables simultaneous compression of multiple data streams, significantly improving data transmission productivity while maintaining clear structural organization through modular design
Solution Approach 2:
The patent ensures continuous operation of multiple compression circuits in parallel, eliminating idle time that occurs in sequential processing. By keeping all compression resources continuously engaged with different data types, the system maximizes data transmission productivity without requiring complex coordination overhead
Data Source
AI summary
A data processing device includes a data selector circuit that divides a plurality of types of data into another plurality of types of data in accordance with a classification of the data, a plurality of compression circuits that respectively compress the plurality of types of data in parallel with each other in accordance with each of the plurality of types of data, and a data transmission circuit that transmits the plurality of types of compressed data to a terminal.