Parallel Data Transfer Circuit With Redundant Group Multiplexing
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Solution Overview
Problem
High-bandwidth data transmission between integrated circuits faces challenges such as signal dissipation and the need for precise clock synchronization, particularly in serialisation-deserialisation (SerDes) applications, where traditional methods like decision-feedback equalization and analogue signal modification are inadequate for achieving low error rates.
Innovation Solution
A digital circuit solution using baud-rate sampling ADCs, feed-forward and decision-feedback equalizers, and a 4-tap FIR filter to pre-compensate for channel impairments, implemented in 65nm CMOS, which performs numerical digital processing to correct channel impairments and improve bit error rate performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional decision-feedback equalization and analogue signal modification are used, then signal transmission is attempted, but error rates remain high and performance is inadequate
Solution Approach 1:
The patent replaces traditional analogue decision-feedback equalization circuits with a digital signal processing approach. The received analogue signal is converted to digital samples by an ADC, then processed using digital filtering and equalization algorithms. This substitution of digital for analogue processing reduces hardware complexity while improving reliability, as digital circuits offer better precision and are more easily optimized for high-speed operation at 12.5 Gb/s.
Solution Approach 2:
The patent employs adaptive equalization where the digital filter coefficients are dynamically adjusted based on the received signal characteristics. The system monitors bit error rates and automatically optimizes equalization parameters such as filter tap weights and decision thresholds. This parameter adaptation enables the system to maintain low error rates across varying channel conditions without increasing fundamental circuit complexity.
2Productivity
If high data rate transmission is implemented, then bandwidth is increased, but signal dissipation and timing synchronization become problematic
Solution Approach 1:
The patent implements pre-emphasis filtering in the digital signal processing chain, where the transmitted signal is pre-distorted to compensate for anticipated channel losses. The digital filter applies frequency-dependent boosting to high-frequency components before transmission, counteracting the high-frequency attenuation that occurs in the transmission medium. This preliminary compensation maintains signal integrity at 12.5 Gb/s without requiring excessive transmit power.
Solution Approach 2:
The system employs continuous feedback mechanisms where the received signal quality is monitored and used to adjust transmission parameters. The digital equalizer adapts its coefficients based on feedback from the channel conditions, and the system can adjust data rate or retransmit corrupted frames. This feedback loop ensures reliable operation at high data rates by dynamically optimizing signal integrity.
3Use of energy by moving object
If digital signal processing is used instead of analogue methods, then power/area scaling is improved, but device complexity increases
Solution Approach 1:
The patent divides the digital signal processing function into modular components: an ADC stage, a digital filter bank with multiple taps, an equalization stage, and a decision device. Each module performs a specific function and can be independently optimized. This segmentation allows efficient resource utilization, where simpler operations (like coefficient multiplication and addition in the filter) are implemented using standard digital logic cells, reducing overall power consumption while managing complexity through functional decomposition.
Data Source
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AI summary
A data transfer circuit is provided for sending digital data at high rates across short but significant distances within an integrated circuit. The data is sent on parallel conductors that are divided into a number of groups. At the receiving end, a multiplexer selects each of the groups in turn and presents them at a set of conductors that are the same in number as one of the groups. At the transmitting end, a data marshalling circuit takes the bitstream to be transmitted and places it on the conductors in a particular redundant fashion so that the bitstream appears to advance across the set of outputs of the multiplexer. That is particularly useful where those outputs are presented to a pre-emphasis filter and line driver. The apparent data rate can be changed by making two or more of the groups of conductors have identical data.