Parallel Data Output Circuit for HiZ Transition Noise Suppression

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Solution Overview

Problem

Existing semiconductor integrated circuits face challenges in accurately transmitting data due to power-supply noise amplification on signal lines, particularly when data output circuits switch from high impedance mode to data transmission mode, affecting both data receiving and transmitting circuits.

Innovation Solution

A semiconductor integrated circuit design that includes data output circuits capable of switching between high impedance and data transmission modes, utilizing a control circuit to output fixed data during mode transitions and select data for transmission, thereby reducing power-supply noise amplification.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If data output circuits switch from high impedance mode to data transmission mode simultaneously, then data transmission efficiency is improved, but power-supply noise amplification occurs

Engineering Contradiction:
Improvedata transmission efficiencyVSAvoidpower-supply noise amplification
Core Design Contradiction:
ProductivityVSObject-affected harmful factors

Solution Approach 1:

The patent applies preliminary action by outputting fixed data (preliminary data) from data output circuits during the transition period before actual data transmission begins. This preliminary output of fixed data prevents simultaneous switching of multiple data output circuits from high impedance mode to data transmission mode, thereby avoiding power-supply noise amplification while maintaining efficient data transmission

Inventive Principle:
Principle #10Preliminary action

2Reliability

If data output circuits output biased data with H or L level voltage, then data transmission capability is maintained, but power-supply noise is amplified

Engineering Contradiction:
Improvedata transmission capabilityVSAvoidpower-supply noise amplification
Core Design Contradiction:
ReliabilityVSObject-affected harmful factors

Solution Approach 1:

The patent implements preliminary action by having data output circuits output fixed data (either H level or L level) during the transition period before actual data transmission. This preliminary output prevents the harmful effect of simultaneous switching and power-supply noise amplification, while still maintaining the ability to transmit data reliably when needed

Inventive Principle:
Principle #10Preliminary action

3Reliability

If ODT function is used to reduce power-supply noise on signal lines, then data receiving circuit performance is improved, but data transmitting circuit noise reduction is not addressed

Engineering Contradiction:
Improvedata receiving circuit performanceVSAvoidcomprehensive noise reduction capability
Core Design Contradiction:
ReliabilityVSAdaptability or versatility

Solution Approach 1:

The patent extends the noise reduction approach by applying preliminary action at the data transmitting circuit side. By outputting fixed data during mode transitions, the invention addresses power-supply noise at its source before it can affect both transmitting and receiving circuits, making the noise reduction capability comprehensive and versatile

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS8653851B2Semiconductor integrated circuit
Publication Date: 2014.02.18 RENESAS ELECTRONICS CORP
  • US8653851B2 patent drawing
  • US8653851B2 patent drawing
  • US8653851B2 patent drawing

AI summary

Provided is a semiconductor integrated circuit according to an exemplary aspect of the present invention including a data transmitting circuit that transmits data in parallel through a plurality of signal lines and a data receiving circuit that receives the data. The data transmitting circuit includes a plurality of data output circuits that output the data in a data transmission mode or set an output to a high impedance state in a HiZ mode, a plurality of data selection circuits that select one of the data and fixed data and output the selected data to the data output circuits, and a control circuit that controls the data output circuits to output the fixed data during a period between a time when a mode is switched from the HiZ mode to the data transmission mode and a time when the data output circuits start to output the data.