Circuit Architecture with Parallel Data Paths for Lower DMA Latency
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Solution Overview
Problem
Existing systems-on-chip (SoCs) experience significant latency and buffer overflow issues due to data traversing multiple bus interconnects and bridges, particularly in DMA operations, leading to undesirable delays and buffer overflows in high-speed serial ports with small internal buffers.
Innovation Solution
Implementing a split-DMA architecture with a master and remote DMA circuit separated by a non-blocking streaming interconnect, reducing the number of hops and ensuring non-blocking communication to minimize latency and buffer overflow.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If data traverses multiple bus interconnects and bridges in traditional DMA operations, then data can be moved between memory devices, but significant latency occurs and buffer overflow issues arise
Solution Approach 1:
The patent divides the traditional single DMA controller into multiple parallel DMA controllers (first DMA circuit and second DMA circuit), each handling separate data paths. This segmentation allows simultaneous data transfers through different routes, reducing latency and preventing buffer overflow by distributing the data transfer load across multiple independent channels rather than forcing all data through a single congested path
Solution Approach 2:
The patent introduces a bridge circuit as an intermediary component that directly connects the first and second memory devices. This bridge acts as a mediator that enables direct data transfer between memory devices without requiring data to traverse through multiple bus interconnects and bridges, thereby reducing latency and eliminating buffer overflow risks associated with traditional multi-hop paths
2Productivity
If a single DMA controller is used to move data through multiple interconnect segments, then data transfer can be performed, but the number of hops increases latency and reduces throughput
Solution Approach 1:
The patent segments the data transfer function into multiple parallel DMA controllers, each capable of independent operation. This allows data to be transferred through multiple concurrent paths simultaneously, increasing overall throughput while reducing the time each individual data transfer takes, as data doesn't need to wait for sequential processing through a single controller
Solution Approach 2:
The patent adds a new dimensional aspect to data transfer by introducing parallel data paths with multiple DMA controllers operating simultaneously. Instead of a single sequential data flow through one DMA controller, the system creates multiple independent data flow dimensions, allowing concurrent transfers that increase productivity without increasing delay
Data Source
AI summary
An integrated circuit (IC) includes first and second memory devices and a bridge. The IC also includes a first interconnect segment coupled between the first memory device and the bridge. The IC further includes a second interconnect segment coupled between the first and second memory devices, and a third interconnect segment coupled between the bridge and the second memory device. The IC includes a first DMA circuit coupled to the first interconnect segment, and a second DMA circuit coupled to the second interconnect segment. A fourth interconnect segment is coupled between the first and second DMA circuits.