Parallel Data Transfer with Post-Correction of Error Portions
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Solution Overview
Problem
Conventional error correction methods in data transfer systems introduce significant processing overhead, power requirements, and delays due to robust error correcting codes and redundant systems, which are inefficient and slow down systems, especially in environments with high error rates and limited power resources.
Innovation Solution
A system and method that utilize a transfer controller to deliver data to a destination memory with concurrent error detection and correction, allowing data to be passed through without delay and corrected post-transfer, using a pass-through section and a correcting section to monitor and regenerate erroneous data portions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If robust error correcting codes and redundant systems are used to address increasing data error rates, then data reliability is improved, but processing overhead, power consumption, and system speed deteriorate
Solution Approach 1:
The patent applies preliminary action by performing error detection and correction in advance during the data transfer process itself, rather than waiting until data reaches the destination. The source controller detects errors using verification features (such as CRC codes) and corrects them before transmission completes, ensuring data reliability while maintaining system speed by preventing post-transfer correction delays
Solution Approach 2:
The patent extracts the error correction function from the destination system and relocates it to the source controller. By taking out the correction burden from the destination end and performing it preliminarily at the source, the system achieves both high reliability (errors corrected before transfer) and high productivity (destination receives ready-to-use data without additional processing overhead)
2Reliability
If multiple independent layers with respective error detection and correction regimes are utilized, then data reliability is improved, but processing overhead and power consumption increase
Solution Approach 1:
The patent merges multiple error detection and correction functions into a single integrated verification feature mechanism. Instead of implementing separate correction regimes at multiple independent layers (source, transmission, destination), the system combines these functions into one unified error detection and correction process performed at the source controller using verification features attached to the data block, thereby reducing power consumption while maintaining reliability
Solution Approach 2:
The verification feature mechanism serves multiple functions simultaneously: it detects errors, enables correction, and validates data integrity all in one process. This multi-functional approach replaces what would otherwise require separate dedicated systems at each layer, reducing overall power consumption while achieving the same reliability goals through a universal error handling mechanism
3Reliability
If very robust error correcting codes are used to protect data payload, then data reliability is improved, but data transfer time and processing delay increase significantly
Solution Approach 1:
The patent performs error detection and correction as a preliminary action during the data transfer process itself, attached to the data block as it is being transmitted. By detecting and correcting errors preliminarily at the source controller using verification features rather than waiting until destination receipt, the system ensures data reliability while minimizing transfer time delays
Solution Approach 2:
The patent skips the traditional multi-layer sequential error correction process by rushing through error detection and correction in a single integrated step at the source controller during transfer. This allows the system to maintain high reliability while significantly reducing the time loss associated with multiple sequential correction layers, as the correction is performed in-line rather than in separate post-processing stages
Data Source
AI summary
A system and method for expeditious transfer of data from a source device to a destination device in error corrected manner are provided. The system and method avoid the substantial delay in utilizing an intermediate buffer, determining error, and remediating the detected errors before even initializing a transfer of an input data from the source device to the destination device. Upon completion of error correction, only those portions corrected are retransmitted to the destination memory rather than the complete corrected input data. A by-pass section is provided for copying input data to the destination memory with at least a degree of parallelism with the error detection of the input data delivered to a parallel buffer coupled with the correction section by a splitter section.