Parallel Data Rate Detection Circuit for Fast Signal Recognition
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Solution Overview
Problem
Existing data rate detection circuits spend excessive time recognizing data rates, leading to potential clock and data recovery failures and suboptimal communication at lower data rates, even when a higher rate is supported by the host.
Innovation Solution
A circuit with multiple data rate detecting units that simultaneously compare multiple alignment patterns corresponding to different data rates to quickly recognize the data rate and ensure communication at the highest supported rate, utilizing a post processing unit to identify the data beginning.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a single data rate detecting unit is used to detect data rate sequentially, then the device complexity is reduced, but the detection time increases leading to clock and data recovery failures
Solution Approach 1:
The data rate detection function is segmented into multiple parallel detecting units, each responsible for a specific data rate. This segmentation allows simultaneous detection of multiple data rates without increasing sequential detection time, resolving the contradiction between simplified structure and fast detection.
Solution Approach 2:
Multiple data rate detecting units are prepared in advance, each pre-configured to detect a specific data rate. When data transmission begins, all units operate simultaneously rather than sequentially, eliminating detection time delays while maintaining structural simplicity through functional specialization.
2Device complexity
If sequential data rate detection is performed, then the device complexity is minimized, but the productivity of data transmission is reduced due to lower data rates being used
Solution Approach 1:
The detection system is divided into multiple specialized units, each optimized for a specific data rate. This enables parallel detection of multiple rates simultaneously, allowing the system to quickly identify and utilize the highest supported data rate, thereby maximizing transmission productivity without complicating the overall device architecture.
Solution Approach 2:
The system changes the operational parameter of data rate detection from sequential to parallel by introducing multiple detecting units. Each unit is tuned to a different data rate parameter, enabling simultaneous detection and allowing the system to select the optimal transmission rate for maximum productivity.
3Speed
If multiple data rate detecting units are used to detect simultaneously, then the data rate detection speed is improved, but the device complexity increases
Solution Approach 1:
The detection function is segmented into multiple independent but specialized units, each handling a specific data rate. This segmentation achieves fast parallel detection while keeping each unit's internal structure simple and manageable, thus improving speed without proportionally increasing overall complexity.
Solution Approach 2:
Multiple data rate detecting units are designed with universal detection logic that can be applied to different data rates. This multi-functionality approach allows the system to achieve high-speed parallel detection across multiple rates while reusing common circuit elements and design patterns, thereby limiting the increase in device complexity.
Data Source
AI summary
A circuit for recognizing a beginning and a data rate of data includes at least two data rate detecting units and a post processing unit. The at least two data rate detecting units are used for comparing at least two alignment patterns corresponding to different data rates with data simultaneously to recognize a data rate of the data. The post processing unit is coupled to the at least two data rate detecting units for recognizing a beginning of the data according to an alignment pattern corresponding to the data when the data rate of the data is recognized.