Parallel Data Storage for Speech DNN Operations
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Solution Overview
Problem
Existing methods for storing data in speech-related deep neural network (DNN) operations fail to ensure continuity, timeliness, and selectivity due to inefficiencies in using general CPUs, DSPs, or GPUs, which result in bandwidth bottlenecks and long operation times.
Innovation Solution
A data storage method that configures peripheral storage access and multi-transmitting interfaces to transport data in parallel, determining configuration parameters such as total frames, skipped frames, and output channels to ensure data continuity and timeliness, reducing the number of memories required and improving data transmission efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If general CPU is used for data storage and retrieval, then data can be stored in peripheral storage device, but data continuity and selectivity cannot be guaranteed due to serial reading and extra calculation programs
Solution Approach 1:
The patent divides the feature storage array into multiple independent memory units (first memory unit, second memory unit, etc.), each capable of storing and transmitting data independently. This segmentation allows parallel access to different data frames, eliminating the serial reading bottleneck of general CPUs and ensuring data continuity while maintaining selectivity through independent memory unit control.
Solution Approach 2:
The patent introduces a new dimension of parallelism by implementing multiple memory units that can simultaneously store and transmit different data frames. This dimensional change from serial to parallel architecture enables simultaneous data access across multiple channels, resolving the contradiction between ease of operation and data reliability.
2Productivity
If GPU or DSP with register file and SIMD form is used, then operations can be performed, but internal storage is limited requiring frequent access to peripheral storage device
Solution Approach 1:
The patent merges the advantages of both peripheral storage devices and internal memory by creating a feature storage array that combines multiple memory units capable of holding large amounts of data locally. This hybrid approach eliminates frequent peripheral storage access while maintaining high-speed operation, as the merged memory structure provides both capacity and speed.
Solution Approach 2:
The patent implements preliminary action by pre-loading data into the feature storage array's multiple memory units before processing is needed. This advance preparation ensures that data is readily available in high-speed memory when required, eliminating the time loss associated with frequent peripheral storage device access while maintaining operational productivity.
3Ease of operation
If serial reading method is used in general CPU, then data can be read from peripheral storage device, but bandwidth bottleneck is created resulting in long operation time
Solution Approach 1:
The patent segments the data transmission path into multiple parallel channels through multiple memory units, each capable of independent data reading and transmission. This segmentation transforms the single-bandwidth serial reading path into multiple parallel paths, eliminating the bandwidth bottleneck and significantly increasing data transmission speed while maintaining ease of operation.
Solution Approach 2:
The patent ensures continuity of useful action by implementing multiple memory units that can simultaneously read and transmit data without interruption. This continuous parallel operation eliminates the idle time and bandwidth constraints of serial reading, maintaining constant high-speed data flow from peripheral storage to processing units.
Data Source
AI summary
A data storage method for speech-related deep neural network (DNN) operations, characterized by comprising the following steps: 1. determining the configuration parameters by a user; 2. configuring a peripheral storage access interface; 3. configuring a multi-transmitting interface of feature storage array; 4. enabling CPU to store to-be-calculated data in a storage space between the feature storage space start address and the feature storage space end address of the peripheral storage device; 5. after data storage, enabling CPU to check the state of the peripheral storage access interface and the multi-transmitting interface of feature storage array; 6. upon receiving a transportation completion signal of the peripheral storage access interface by CPU, enabling the multi-transmitting interface of feature storage array. 7. upon receiving a transportation completion signal of the multi-transmitting interface of feature storage array by CPU, repeating step 6.