Parallel Data Switch Logic Triplet Priority Routing
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Solution Overview
Problem
Existing interconnect systems in large computing and communication systems face challenges in achieving high port counts with low latency and high bandwidth, particularly in handling short packets efficiently.
Innovation Solution
The interconnect apparatus comprises a plurality of logic units arranged in triplets with priority settings, utilizing parallel buses and one-bit-long FIFOs at each level to enable faster clock rates and improved signal integrity, allowing for higher bandwidth and reduced latency by prioritizing data paths and using advanced routing logic.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If the switch-chip port count is increased, then the number of chip-to-chip hops decreases resulting in lower latency, but the ability to handle short packets efficiently deteriorates
Solution Approach 1:
The packet handling function is segmented into multiple parallel logic units (LA, LB, LC, LD) that can independently process different packets or packet segments simultaneously. Each logic unit can handle short packets independently, eliminating the bottleneck that would occur in sequential processing and maintaining high efficiency even as port count increases
Solution Approach 2:
The system dynamically selects which logic unit processes each packet based on current conditions. The patent implements dynamic routing where packets can be directed to different logic units (LA or LC) depending on availability and priority, allowing the system to adapt to varying traffic patterns and maintain optimal short packet handling efficiency regardless of port count
2Productivity
If parallel data paths are used to increase bandwidth, then more data can be transmitted simultaneously, but signal integrity deteriorates at high clock rates
Solution Approach 1:
The parallel data paths are segmented into distinct logic units with dedicated communication channels. Each logic unit (LA, LB, LC, LD) has its own input/output paths, preventing signal interference that would occur in shared high-speed paths. This segmentation maintains signal integrity while still providing parallel processing capability for high bandwidth
Solution Approach 2:
The patent introduces intermediary control logic and buffering mechanisms between parallel data paths. These intermediaries regulate data flow, synchronize timing, and prevent signal conflicts, allowing multiple parallel paths to operate simultaneously without degrading signal integrity even at high clock rates
3Loss of time
If logic units are arranged in triplets with priority settings, then data paths can be prioritized to reduce latency, but device complexity increases
Solution Approach 1:
The logic units are arranged in an asymmetric triplet configuration (LA, LC, LD) with clearly defined priority relationships. Logic unit LC has priority over LA for accessing LD, creating an asymmetric but simple priority structure. This asymmetric design reduces the complexity of arbitration logic compared to symmetric multi-unit configurations, as the priority rules are fixed and straightforward rather than requiring complex dynamic arbitration
Data Source
AI summary
An interconnect apparatus enables improved signal integrity, even at high clock rates, increased bandwidth, and lower latency. An interconnect apparatus can comprise a plurality of logic units and a plurality of buses coupling the plurality of logic units in a selected configuration of logic units arranged in triplets comprising logic units LA, LC, and LD. The logic units LA and LC are positioned to send data to the logic unit LD. The logic unit LC has priority over the logic unit LA to send data to the logic unit LD. For a packet PKT divided into subpackets, a subpacket of the packet PKT at the logic unit LA, and the packet specifying a target either: (A) the logic unit LC sends a subpacket of the packet PKT to the logic unit LD and the logic unit LA does not send a subpacket of the packet PKT to the logic unit LD; (B) the logic unit LC does not send a subpacket of data to the logic unit LD and the logic unit LA sends a subpacket of the packet PKT to the logic unit LD; or (C) the logic unit LC does not send a subpacket of data to the logic unit LD and the logic unit LA does not send a subpacket of the packet PKT to the logic unit LD.