Parallel Data Switch Logic Triplet Priority Interconnect
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Solution Overview
Problem
Existing interconnect systems in large computing and communication systems face challenges in achieving high port counts, handling short packets efficiently, and maintaining low latency while supporting high clock rates.
Innovation Solution
The interconnect apparatus comprises a plurality of logic units arranged in triplets with specific configurations, where logic unit LC has priority over logic unit LA to send data to logic unit LD, utilizing parallel buses and one-tick FIFOs to enable faster data transmission and increased bandwidth.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If the switch-chip port count is increased to decrease the number of chip-to-chip hops, then latency is reduced and cost is reduced, but the ability to handle short packets efficiently deteriorates
Solution Approach 1:
The patent segments packets into subpackets that can be processed and transmitted in parallel through multiple logic units. This segmentation allows short packets to be handled efficiently by distributing them across multiple processing paths, resolving the contradiction between high port count architecture and short packet handling capability
Solution Approach 2:
The patent implements dynamic priority assignment where logic units can be configured with different priority levels (e.g., LC has priority over LA) based on traffic conditions and packet types. This dynamic configuration allows the system to adapt to different packet lengths and traffic patterns, maintaining efficiency for both short and long packets while utilizing the high port count architecture
2Productivity
If parallel data paths are implemented to increase bandwidth, then data transmission capacity is improved, but signal integrity deteriorates at high clock rates
Solution Approach 1:
The patent introduces priority logic units and control mechanisms as intermediaries that manage data flow through the parallel paths. These intermediaries coordinate transmission timing and prioritize critical data, preventing signal conflicts and maintaining integrity while utilizing multiple parallel paths for high bandwidth
Solution Approach 2:
The patent changes operational parameters by implementing one-tick FIFOs and priority-based scheduling that optimize timing and data flow characteristics. These parameter changes allow the system to maintain signal integrity at high clock rates while utilizing parallel paths for increased bandwidth
3Productivity
If logic unit LC is given priority over logic unit LA to send data to logic unit LD, then bandwidth is increased, but the complexity of priority management increases
Solution Approach 1:
The patent applies local quality by implementing priority rules at specific logic unit interfaces (LC to LD) rather than system-wide complex arbitration. The priority relationship is localized to specific data paths, simplifying overall management while still achieving high bandwidth through optimized critical path transmission
Data Source
AI summary
An interconnect apparatus enables improved signal integrity, even at high clock rates, increased bandwidth, and lower latency. An interconnect apparatus can comprise a plurality of logic units and a plurality of buses coupling the plurality of logic units in a selected configuration of logic units arranged in triplets comprising logic units LA, LC, and LD. The logic units LA and LC are positioned to send data to the logic unit LD. The logic unit LC has priority over the logic unit LA to send data to the logic unit LD. For a packet PKT divided into subpackets, a subpacket of the packet PKT at the logic unit LA, and the packet specifying a target either: (A) the logic unit LC sends a subpacket of the packet PKT to the logic unit LD and the logic unit LA does not send a subpacket of the packet PKT to the logic unit LD; (B) the logic unit LC does not send a subpacket of data to the logic unit LD and the logic unit LA sends a subpacket of the packet PKT to the logic unit LD; or (C) the logic unit LC does not send a subpacket of data to the logic unit LD and the logic unit LA does not send a subpacket of the packet PKT to the logic unit LD.