Parallel DDFSE Pipeline With Edge Correction for ISI Decoding
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Solution Overview
Problem
In high-speed data communications, the Viterbi decoder's large number of states due to Inter-symbol Interference (ISI) makes circuit implementation impractical, especially when processing binary data across multiple symbols, limiting processing speed and feasibility.
Innovation Solution
A delayed decision feedback sequence estimator is used, dividing received data into blocks and employing (L+M) DDFSE computing units operating at a reduced clock rate for parallel processing, along with an edge effect detection-correction circuit to prevent error rate deterioration, enabling faster processing without the upper bound limitations of conventional feedback loops.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a Viterbi decoder is used to perform maximum likelihood sequence estimation when ISI occurs across many symbols, then the best error rate can be theoretically realized, but the number of states becomes very large making circuit implementation infeasible
Solution Approach 1:
The patent segments the received data into multiple blocks and processes each block independently using separate DDFSE computing units. This segmentation allows parallel processing of multiple data blocks simultaneously, increasing throughput while keeping each processing unit's state complexity manageable. The segmentation divides the overall complex estimation task into smaller, parallelizable sub-tasks.
Solution Approach 2:
The patent introduces a new dimension of parallel processing by using multiple DDFSE computing units operating in parallel on different data blocks. Instead of increasing the processing speed of a single unit, the solution adds processing capacity through multiple units working simultaneously, effectively solving the throughput limitation without requiring higher clock rates.
2Loss of time
If the feedback loop is shortened by performing tap calculation in advance, then processing time is reduced, but the upper bound of processing speed is still determined by the feedback loop configuration
Solution Approach 1:
The patent segments the data processing into independent blocks that can be processed in parallel. Each block is handled by a separate DDFSE computing unit, eliminating the sequential dependency that limits overall processing speed. This segmentation allows the system to process multiple blocks simultaneously, achieving higher throughput despite the feedback loop's inherent time requirements.
Solution Approach 2:
The patent combines multiple DDFSE computing units into a single system that processes multiple data blocks in parallel. By merging the capabilities of multiple units, the system achieves higher overall processing speed and throughput, overcoming the limitation of individual feedback loop processing speeds.
3Productivity
If received data is divided into blocks for parallel processing, then processing throughput is improved, but error rate deterioration occurs at block boundaries
Solution Approach 1:
The patent applies preliminary actions by pre-calculating and storing tap coefficients before processing each data block. This preliminary preparation allows the DDFSE computing units to process blocks more efficiently without compromising accuracy. Additionally, the system performs edge effect detection and correction as a preliminary step to identify and mitigate potential error rate deterioration at block boundaries.
Solution Approach 2:
The patent implements feedback mechanisms through edge effect detection and correction circuits that monitor the processing output. When error rate deterioration is detected at block boundaries, the feedback system activates correction measures to restore accuracy. This feedback loop ensures that the benefits of parallel block processing are maintained without sacrificing reliability.
Data Source
AI summary
Disclosed is a delayed decision feedback sequence estimator comprising a delayed decision feedback sequence estimator main unit including DDFSE computing unit group including (L+M) DDFSE computing units, equal in number to a length of each of plurality of blocks into which a received data symbol sequence is divided; wherein (L+M) DDFSE computing units are connected in a pipeline configuration to execute delayed decision feedback sequence estimation of the blocks in parallel; and an edge effect detection and correction circuit that detects an edge effect due to processing the delayed decision feedback sequence estimation of the separated block and corrects a relevant bit error.