Parallel Decision Tree Classification Using Flag LUT Architecture

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Solution Overview

Problem

Conventional decision trees are not well-suited for parallel processing, particularly in high-computational and high-speed applications, due to serial navigation requirements and issues with pipelined processing flow changes, leading to inefficiencies in evaluating and classifying data.

Innovation Solution

A decision tree architecture using a look-up table with n-bit words and distributed test units across multiple processing engines, allowing for independent evaluation of all nodes and flexible computation sequences, eliminating the need for serial processing and simplifying massively parallel systems.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If conventional decision trees are processed serially, then the processing flow is simple to implement, but the processing speed and throughput are limited

Engineering Contradiction:
Improveprocessing speedVSAvoidprocessing architecture complexity
Core Design Contradiction:
SpeedVSDevice complexity

Solution Approach 1:

The decision tree evaluation is segmented into independent node evaluations, where each node can be processed by a separate processing element. This allows parallel execution of multiple node evaluations simultaneously, dramatically increasing processing speed while maintaining manageable architectural complexity through modular design

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent transitions from sequential single-dimensional processing to multi-dimensional parallel processing by distributing node evaluations across multiple processing elements in a parallel architecture, enabling simultaneous evaluation of multiple decision nodes along different paths in the decision tree

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Productivity

If decision trees are evaluated using pipelined processing, then throughput is improved, but changes to processing flow cause inefficiencies and performance degradation

Engineering Contradiction:
ImprovethroughputVSAvoidprocessing flow adaptability
Core Design Contradiction:
ProductivityVSAdaptability or versatility

Solution Approach 1:

The patent implements a dynamic processing architecture where processing elements can adaptively execute different node evaluations based on data characteristics and decision tree structure. This dynamic approach allows the system to maintain high throughput while flexibly adapting to changes in processing flow requirements without the rigid constraints of fixed pipelining

Inventive Principle:
Principle #15Dynamics

3Productivity

If massively parallel processing is implemented, then computational efficiency is improved, but the architecture becomes more complex and difficult to manage

Engineering Contradiction:
Improvecomputational efficiencyVSAvoidarchitecture complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent employs universal processing elements that can evaluate any decision node regardless of its position or type in the decision tree. This multi-functionality allows massively parallel processing to be achieved with uniform, simple processing units, reducing architectural complexity while maintaining high computational efficiency through scalable parallelism

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentEP3422245B1Methods, processing engines, and microprocessors for classifying data according to decision trees
Publication Date: 2022.02.16 NXP USA INC
  • EP3422245B1 patent drawingFigure 1
  • EP3422245B1 patent drawingFigure 2~3
  • EP3422245B1 patent drawingFigure 4~5

AI summary

A processing engine for classifying data according to a decision tree having n-nodes is disclosed, wherein each node is represented by a respective test according to which a flag may be set or unset, comprising: a respective test unit and corresponding to each node, having an output flag and being configured to set or unset the respective output flag according to an output of the respective test; a memory configured to hold an n-bit word, each bit corresponding to a one of the respective output flags; and a data-structure configured as a look up table, each entry of the look up table representing a class of the data. Corresponding methods are also disclosed, as are devices and systems incorporating such processing engines.