Parallel Decision Tree Processor Architecture for High-Speed Scoring
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Solution Overview
Problem
Conventional software-based decision tree scoring methods are inefficient, leading to slower processing times and increased bandwidth and storage requirements in applications such as document ranking and gesture recognition.
Innovation Solution
A hardware implementation of decision tree scoring using specialized or programmable logic circuits with parallel decision tree processors, feature value and threshold value compression, and multi-threaded, pipelined tree walking to reduce bandwidth and storage needs while enhancing processing speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If software-based decision tree scoring is used, then implementation simplicity is maintained, but processing speed is slow
Solution Approach 1:
The patent replaces software-based decision tree scoring with a specialized hardware processor that executes decision tree operations in parallel. The hardware implementation uses dedicated circuits for feature comparison, threshold evaluation, and tree traversal, substituting the sequential software execution model with concurrent hardware operations, thereby achieving significant speedup while managing complexity through architectural specialization.
2Productivity
If parallel decision tree processors are implemented, then processing speed increases, but device complexity increases
Solution Approach 1:
The patent divides the decision tree processing system into multiple independent processor units, each capable of handling specific decision trees or feature comparisons simultaneously. This segmentation enables parallel processing of multiple decision trees across different processor units, increasing overall throughput while keeping individual unit complexity manageable through modular design.
Solution Approach 2:
The patent designs processor units with universal functionality to handle various decision tree operations including feature comparison, threshold evaluation, and tree traversal. Each processor unit can be configured to execute different decision trees through programmable logic, providing multi-functionality that increases productivity without proportionally increasing hardware complexity.
3Quantity of substance
If feature value and threshold value compression is applied, then storage requirements are reduced, but data access complexity increases
Solution Approach 1:
The patent applies compression techniques that transform feature values and threshold values into compressed representations with fewer bits. This parameter transformation reduces the quantity of data that needs to be stored and transmitted while maintaining the ability to perform accurate comparisons. The compression is integrated into the hardware architecture, managing access complexity through dedicated decompression logic.
Data Source
AI summary
A decision tree multi-processor system includes a plurality of decision tree processors that access a common feature vector and execute one or more decision trees with respect to the common feature vector. A related method includes providing a common feature vector to a plurality of decision tree processors implemented within an on-chip decision tree scoring system, and executing, by the plurality of decision tree processors, a plurality off decision trees, by reference to the common feature vector. A related decision tree-walking system includes feature storage that stores a common feature vector and a plurality of decision tree processors that access the common feature vector from the feature storage and execute a plurality of decision trees by comparing threshold values of the decision trees to feature values within the common feature vector.