Parallel Decode Circuits for Network-on-Chip Latency
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Solution Overview
Problem
Network-on-chip (NoC) systems face latency issues due to sequential address decode and packet arbitration processes, which hinder efficient communication between cores and logic blocks, especially in complex multicore processors where bandwidth requirements demand improved interconnect architectures.
Innovation Solution
Implementing parallel address decode and packet arbitration in routers within the NoC system, where direction decoding occurs in parallel with packet arbitration, reducing latency by removing sequential dependencies and improving resource utilization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If sequential address decode and packet arbitration are used in routers, then device complexity is reduced, but network latency increases
Solution Approach 1:
The address decode operation is performed in advance during the packet arbitration phase, so that when the arbitration is complete, the decode result is already available. This eliminates the sequential dependency where decode must wait for arbitration to finish, thereby reducing network latency without significantly increasing router complexity.
Solution Approach 2:
The patent transforms the sequential execution model into a parallel execution model by introducing a temporal dimension - performing address decode and packet arbitration simultaneously in different phases of the same clock cycle. This dimensional transformation allows both operations to complete faster overall, reducing latency while maintaining manageable complexity.
2Productivity
If parallel address decode and packet arbitration are implemented, then network latency is reduced, but device complexity increases
Solution Approach 1:
The router operation is segmented into distinct phases within a clock cycle: the packet arbitration phase where address decode is preliminarily performed, and the forwarding phase where the decoded address is used. This segmentation allows parallel operations to be organized systematically, improving communication efficiency while controlling complexity through structured phase separation.
Solution Approach 2:
The address decode logic is designed to serve multiple purposes: it determines the destination router for packet forwarding, and simultaneously provides address information for routing decisions. This multi-functionality allows the same hardware structure to support both decode and arbitration functions, improving productivity without proportionally increasing device complexity.
Data Source
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AI summary
A first packet and a first direction associated with the first packet are received. The first packet is forwarded to an output port of a plurality of output ports of the first router based on the first direction associated with the first packet. A second direction associated with the first packet is determined. The second direction is based at least on an address of the first packet. The first packet and the second direction are forwarded through the output port of the first router to a second router.