Parallel Decoder Sampling for Accurate Low-Power Signal Reception
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing data processing systems face challenges in accurately receiving signals due to non-ideal factors like channel effects and clock jitter, which require increasing the sampling rate, leading to power consumption issues and implementation difficulties.
Innovation Solution
A data processing device and method utilizing multiple decoder circuits to perform parallel decoding by setting groups of sampling points based on an initial transition edge of a signal, generating multiple signals for checking, and selecting the appropriate decoder circuit for subsequent data reception based on the check result.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the sampling rate is increased to tolerate errors from non-ideal factors, then the signal receiving accuracy is improved, but the power consumption of the receiver circuit is significantly increased
Solution Approach 1:
The invention divides the decoding process into multiple segments by using multiple decoder circuits (first decoder circuit and second decoder circuit) that operate in parallel with different sampling points. This segmentation allows the system to achieve better error tolerance through diversity without requiring a uniform increase in sampling rate across the entire system, thereby avoiding proportional power consumption increase.
Solution Approach 2:
The invention changes the sampling parameters (sampling points) across different decoder circuits rather than uniformly increasing the sampling rate. The first decoder circuit uses first sampling points while the second decoder circuit uses second sampling points, allowing the system to tolerate errors through parameter diversity without the power consumption penalty associated with higher sampling rates.
2Measurement precision
If the sampling rate is increased to process signals with errors, then the signal receiving accuracy is improved, but the implementation difficulty is significantly increased
Solution Approach 1:
The system segments the decoding function into multiple independent decoder circuits that can be implemented using standard sampling rates. This segmentation approach avoids the need for high-speed sampling circuitry, making the implementation more feasible with current manufacturing capabilities while still achieving improved accuracy through parallel processing and diversity combining.
3Measurement precision
If multiple decoder circuits are used to perform parallel decoding, then the signal receiving accuracy is improved, but the device complexity is increased
Solution Approach 1:
The multiple decoder circuits are designed with identical structures and functions, each capable of performing the complete decoding process independently. This universality allows the system to achieve improved accuracy through parallel processing while maintaining modular, repeatable circuit designs that can be efficiently implemented and managed, offsetting the apparent complexity through standardization.
Solution Approach 2:
The checker circuit provides feedback by checking the output signals from multiple decoder circuits and determining which decoding result is valid. This feedback mechanism automatically selects the correct decoded signal without requiring complex error correction algorithms, simplifying the overall system architecture while maintaining high accuracy.
Data Source
AI summary
A data processing device includes decoder circuits, a checker circuit, and a control circuit. The decoder circuits set groups of first sampling points and groups of second sampling points according to an initial transition edge of a first signal, and perform a parallel decoding on the first signal according to the groups of first sampling points and the groups of second sampling points, in order to generate a second signal and a third signal. The checker circuit checks the second signal and the third signal, in order to generate a check result. The control circuit selects at least one of the decoder circuits according to the check result for receiving subsequent data.