Electronic Device Parallel Decoding for Faster Boot
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Solution Overview
Problem
Poor decompression efficiency in electronic devices leads to slow booting and degraded user experience due to the computing circuit's inability to efficiently decompress compressed files, particularly during the booting process.
Innovation Solution
The electronic device employs a decompression module with multiple decoding circuits that segment compressed data into sub-blocks, allowing simultaneous decoding and data alignment to improve decompression efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a single decoding circuit is used to decompress compressed files, then the device complexity is low, but the decompression efficiency is poor leading to slow booting
Solution Approach 1:
The decompression module is divided into multiple independent decoding circuits (first decoding circuit, second decoding circuit, etc.), each responsible for decoding specific sub-blocks of compressed data. This segmentation enables parallel processing and improves decompression efficiency while keeping each individual circuit relatively simple.
Solution Approach 2:
The patent introduces a temporal dimension to the decoding process by using multiple decoding circuits that operate simultaneously on different data segments. Instead of sequential decoding (single circuit over time), the system uses parallel decoding (multiple circuits at the same time), effectively adding a dimension to the processing architecture.
2Loss of time
If compressed data is decompressed sequentially in the storage device, then the device complexity is low, but the boot time increases
Solution Approach 1:
The compressed data is divided into multiple sub-blocks, and multiple decoding circuits are assigned to decode these sub-blocks simultaneously. This segmentation and parallel processing approach significantly reduces the total decompression time, directly addressing the boot time issue.
Solution Approach 2:
The system prepares multiple decoding circuits in advance and assigns them to different sub-blocks before the actual decompression process starts. This preliminary setup enables immediate parallel decoding operation, reducing the overall time loss during booting.
3Productivity
If multiple decoding circuits are used to decode compressed data simultaneously, then the decompression efficiency is improved, but the device complexity increases
Solution Approach 1:
The decompression module is divided into multiple independent decoding circuits (first decoding circuit, second decoding circuit, etc.), each responsible for decoding specific sub-blocks of compressed data. This segmentation enables parallel processing and improves decompression efficiency while keeping each individual circuit relatively simple.
Solution Approach 2:
Each decoding circuit in the patent is designed with universal functionality to handle different types of compressed data and can be configured for different decoding tasks. This multi-functionality reduces the need for specialized complex circuits for each decoding scenario, maintaining simplicity while achieving high productivity.
Data Source
AI summary
An electronic device includes a first and second decoding circuits and is coupled to a storage device and a memory, and the storage device stores compressed data. An operation method of the electronic device includes the following steps: performing a first read operation to read a first sub-block from a first read address of the storage device; performing a first write operation to write the first sub-block to a first write address of the memory; performing a second read operation to read a second sub-block from a second read address of the storage device; performing a second write operation to write the second sub-block to a second write address of the memory; reading via the first decoding circuit the first sub-block from the memory and decoding via the first decoding circuit the first sub-block; and reading via the second decoding circuit the second sub-block from the memory and decoding via the second decoding circuit the second sub-block.