Parallel Decoding Cores with On-Chip Buffers for Memory Bandwidth Reduction
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Solution Overview
Problem
High-speed image decoding processes face performance limitations due to high access speeds required for reference raster memory, leading to bandwidth consumption and cost issues in shared memory systems, especially when processing high-resolution images.
Innovation Solution
An image decoding apparatus with two decoding cores that operate in parallel, using small-capacity buffers to smooth input and output flow rates, reducing access to external memory by storing reference data and compression codes, and employing round robin scheduling for arbitration control to optimize data transfer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If reference raster memory is accessed at high speed for each pixel decoding, then decoding speed is improved, but memory bandwidth consumption increases and system cost increases
Solution Approach 1:
The decoding system is divided into multiple independent decoding cores (first decoding core, second decoding core) that operate in parallel. Each core processes different portions of the image data, allowing the system to achieve high decoding speeds without requiring each core to access reference raster memory at full speed, thereby reducing overall memory bandwidth consumption.
Solution Approach 2:
Reference raster data is pre-loaded into on-chip buffers before decoding operations begin. This preliminary action allows decoding cores to access reference data from fast on-chip memory rather than from external memory during the actual decoding process, maintaining high decoding speed while reducing external memory bandwidth requirements.
2Speed
If on-chip reference raster memory capacity is increased to store full reference data, then decoding speed is improved, but chip size and cost increase
Solution Approach 1:
The reference raster storage is segmented into multiple small-capacity buffers distributed across different decoding cores rather than using one large centralized memory. This segmentation allows each core to have its own small buffer, reducing the total on-chip memory capacity needed while maintaining high decoding speed through parallel access.
Solution Approach 2:
Instead of loading the entire reference raster into on-chip memory, only the necessary portions of reference data are pre-loaded into small buffers. This partial action approach provides sufficient reference data for decoding operations without requiring large on-chip memory capacity, thus reducing chip size and cost.
3Productivity
If multiple decoding cores operate in parallel, then productivity is improved, but device complexity increases
Solution Approach 1:
The parallel decoding system is segmented into identical, independent decoding cores with uniform structures. Each core has the same functional units and buffer configurations, which simplifies the overall system design compared to using heterogeneous cores. This segmentation into identical units increases productivity through parallelism while minimizing the complexity increase.
Solution Approach 2:
Multiple decoding cores are merged into a unified parallel processing architecture that shares common control logic and buffer management mechanisms. This merging approach allows the system to achieve high throughput through parallelism while reducing complexity by consolidating control functions rather than having separate control logic for each core.
4Loss of energy
If small-capacity buffers are used to smooth input/output flow, then memory access requirements are reduced, but buffer management complexity increases
Solution Approach 1:
Buffers are pre-configured with predetermined capacities that are sufficient to smooth the input and output flow rates for typical decoding operations. This preliminary configuration eliminates the need for complex runtime buffer management and allocation logic, reducing memory access requirements while keeping buffer management simple through fixed-size pre-configured buffers.
Data Source
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AI summary
An image decoding apparatus which decodes externally received encoded image information includes a storage unit (104) which stores the image information. The image decoding apparatus includes a first decoding unit (203) which receives, from the storage unit, image data to be decoded and reference data, and decodes the target image data. The image decoding apparatus includes a second decoding unit (204) which receives the image data decoded by the first decoding unit, receives, from the storage unit, image data to be decoded based on the decoded image data, and decodes the image data received from the storage unit. The image decoding apparatus includes a decoding control unit (205) which controls the first and second decoding units to repetitively execute decoding of image data in parallel.