Parallel Instruction Decoding With Switch Tags and Micro-Op Cache
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Solution Overview
Problem
Existing processor architectures face challenges in efficiently decoding instructions due to limitations in throughput and complexity when using multiple decoder groups for parallel decoding, particularly in managing instruction allocation and micro-op merging to maintain the instruction fetching order.
Innovation Solution
A processor architecture that utilizes a switch tag in the instruction fetching request to indicate instruction positions for decoder group switching, allowing parallel decoding across multiple decoder groups, and supports both decoder and micro-op cache modes for efficient micro-op acquisition.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple decoder groups are used for parallel decoding, then decoding throughput is improved, but device complexity increases due to instruction allocation and micro-op merging management
Solution Approach 1:
A switch tag mechanism is introduced as an intermediary to manage decoder group switching. The switch tag is attached to instructions at specific positions and guides the allocation of instruction streams to appropriate decoder groups, automating the complex management of parallel decoding without requiring complex control logic
Solution Approach 2:
The instruction stream is segmented into multiple segments that can be independently decoded by different decoder groups. The switch tag indicates where segmentation should occur, allowing the instruction stream to be divided and distributed to multiple decoder groups for parallel processing
2Stability of the object's composition
If decoder group switching is implemented to maintain instruction fetching order, then micro-op sequence consistency is improved, but decoding complexity increases
Solution Approach 1:
Switch tags are pre-attached to instructions at positions where decoder group switching should occur, before the actual decoding process. This preliminary marking simplifies the decoding complexity by providing advance guidance on how to allocate instruction streams to maintain proper micro-op sequence consistency
Solution Approach 2:
The switch tag acts as an intermediary marker that carries decoding mode information through the instruction stream. It mediates between the instruction fetching unit and decoder groups, enabling automatic switching without complex control logic
3Productivity
If micro-op cache mode is supported in addition to decoder mode, then decoding efficiency is improved through caching, but device complexity increases
Solution Approach 1:
The decoding system is designed with multi-functionality to support both decoder mode and micro-op cache mode. The same instruction fetching and allocation infrastructure can operate in either mode, with the micro-op cache providing an additional optimization layer without requiring separate dedicated paths
Data Source
Figure 1A~1B
Figure 2A~2B
Figure 2C
AI summary
Embodiments of the present disclosure provide a decoding method, a processor, a chip, and an electronic device. The method comprises: generating an instruction fetch request carrying at least one switching mark, the switching mark at least indicating an instruction position for decoder group switching; in response to micro-ops obtained from decoding by decoder groups, acquiring an instruction stream fetched by means of the instruction fetch request, and according to the switching mark carried in the instruction fetch request, determining the instruction position for decoder group switching; according to the instruction position, distributing the instruction stream to multiple decoder groups for parallel decoding, and carrying a switching mark in a target micro-op obtained by decoding a target instruction, the target instruction being an instruction corresponding to the instruction position; and in response to searching a micro-op cache for micro-ops, if the instruction fetch request is hit in the micro-op cache, acquiring a corresponding micro-op from the micro-op cache. The embodiments of the present disclosure can improve the decoding performance of a processor.