Parallel Delay-Chain Measurement Circuit for Faster TDC Sampling
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Solution Overview
Problem
Measurement circuits, such as time-to-digital converters, face limitations in dynamic range and measurement granularity due to longer delay chains, which result in increased propagation delay and reduced attainable dynamic range.
Innovation Solution
A multi-chain measurement circuit design featuring parallel delay chains with serially-connected buffer circuits and storage circuits that capture logic values to produce a digital output indicative of the number of buffer circuits through which an input signal has propagated, allowing for wider dynamic range and higher granularity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a single long delay chain is used to increase measurement dynamic range, then measurement granularity is improved, but propagation delay increases and measurement throughput decreases
Solution Approach 1:
The patent divides a single long delay chain into multiple parallel delay chains (e.g., four chains with 16 stages each instead of one chain with 64 stages). Each chain processes a portion of the measurement range, allowing signals to propagate through shorter paths while maintaining the total measurement dynamic range through parallel operation and digital aggregation of results.
2Measurement precision
If a single long delay chain is used to increase measurement dynamic range, then measurement granularity is improved, but measurement throughput decreases
Solution Approach 1:
The patent divides a single long delay chain into multiple parallel delay chains (e.g., four chains with 16 stages each instead of one chain with 64 stages). Each chain processes a portion of the measurement range, allowing signals to propagate through shorter paths while maintaining the total measurement dynamic range through parallel operation and digital aggregation of results.
Solution Approach 2:
The patent implements pipelined operation where multiple measurements can be processed simultaneously across different delay chains and clock cycles. While one chain is capturing a measurement, other chains are already processing subsequent measurements, eliminating idle time and maintaining continuous measurement throughput.
3Productivity
If parallel delay chains are used to reduce propagation delay, then measurement throughput is improved, but circuit complexity increases
Solution Approach 1:
The patent designs identical delay chain units that can be replicated multiple times to form parallel chains. Each chain unit serves multiple functions: signal propagation, delay generation, and measurement capture. This modular approach manages complexity by using repeated standard cells rather than designing unique complex circuitry for each parallel path.
Solution Approach 2:
The patent combines the output signals from multiple parallel delay chains through digital logic that aggregates the individual chain results into a unified measurement value. This merging process consolidates the complexity of multiple parallel operations into a single digital output, managing system complexity while maintaining the throughput benefits of parallel operation.
Data Source
AI summary
A multi-chain measurement circuit is disclosed. The measurement circuit includes first and second chains of serially-connected buffer circuits coupled in parallel, each of which propagates an input signal. A set of storage circuits is configured to store logic values generated by the first and second sets of buffer circuits in response to the transitioning of a clock signal. The logic values stored in the storage circuits result in a digital value indicative of a total number of serially-connected storage circuits through which the input signal has propagated at the time of the transition of the operating clock signal.