Parallel Delay-Chain Measurement Circuit for Faster TDC Resolution
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Solution Overview
Problem
Existing measurement circuits, such as time-to-digital converters (TDCs), face limitations in dynamic range and measurement granularity due to the propagation delay in longer delay chains, which restricts their application in detecting voltage droops and other measurements.
Innovation Solution
A multi-chain measurement circuit is introduced, featuring first and second delay circuits connected in parallel, each comprising serially-connected buffer circuits. Storage circuits capture logic values from these buffers in response to a clock signal, allowing the circuit to output a digital value indicative of the total number of buffer circuits through which the input signal has propagated.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a single delay chain with more buffer circuits is used to increase measurement dynamic range, then measurement resolution is improved, but propagation delay increases and measurement throughput decreases
Solution Approach 1:
The measurement circuit is divided into multiple parallel delay chains (first delay chain with first plurality of buffers, second delay chain with second plurality of buffers) instead of using a single long delay chain. Each chain processes signals independently and simultaneously, allowing the circuit to achieve the resolution equivalent of a longer chain while maintaining shorter propagation delay through parallel processing.
2Adaptability or versatility
If a single delay chain is used, then device complexity is low, but measurement dynamic range and granularity are limited
Solution Approach 1:
The circuit transitions from a one-dimensional single delay chain to a two-dimensional multi-chain parallel structure. By adding the dimension of parallelism with multiple delay chains operating simultaneously, the circuit achieves expanded measurement dynamic range and granularity without proportionally increasing complexity, as the chains share common input/output infrastructure and control logic.
Data Source
AI summary
A multi-chain measurement circuit is disclosed. The measurement circuit includes first and second chains of serially-connected buffer circuits coupled in parallel, each of which propagates an input signal. A set of storage circuits is configured to store logic values generated by the first and second sets of buffer circuits in response to the transitioning of a clock signal. The logic values stored in the storage circuits result in a digital value indicative of a total number of serially-connected storage circuits through which the input signal has propagated at the time of the transition of the operating clock signal.