Parallel Delay Line Using Split Signal Paths for Precise Timing
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Solution Overview
Problem
Automated test equipment (ATE) faces challenges in accurately coordinating the timing of test signals due to differences in propagation delays, affecting the accuracy of electronic component testing.
Innovation Solution
A signal delay apparatus and method using a splitter circuit to split high-speed input signals into lower-speed split signals, which are then delayed in parallel paths and recombined to generate a delayed signal with adjustable timing, allowing for calibration to compensate for propagation delays.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If traditional delay lines are used to coordinate test signal timing, then timing accuracy can be improved, but power consumption increases and device complexity increases
Solution Approach 1:
The input signal is divided into multiple parallel paths, each processing a portion of the data. By segmenting the signal processing into parallel lower-speed paths rather than a single high-speed path, the system achieves accurate timing coordination while reducing power consumption and complexity in each individual path.
2Measurement precision
If traditional delay lines are used to coordinate test signal timing, then timing accuracy can be improved, but device complexity increases
Solution Approach 1:
The circuit is divided into multiple parallel delay paths with identical structures. Each path processes a segment of the input signal independently. This segmentation approach reduces the complexity of individual paths while maintaining overall timing accuracy through parallel processing and combination of results.
3Speed
If high-speed signals are processed directly, then data rate is maintained, but timing accuracy and power efficiency deteriorate
Solution Approach 1:
The high-speed input signal is segmented into parallel paths that operate at lower speeds. Each parallel path processes its portion at a reduced data rate, which improves timing accuracy and power efficiency. The parallel paths are then combined to reconstruct the original high-speed signal, maintaining both speed and accuracy.
4Speed
If high-speed signals are processed directly, then data rate is maintained, but power consumption increases
Solution Approach 1:
The high-speed signal processing is segmented into multiple parallel lower-speed paths. By dividing the processing workload across parallel paths operating at lower speeds, the overall power consumption is reduced while maintaining the original data rate through parallel processing and signal combination.
Data Source
AI summary
Circuitry and methods of operating the same to delay a signal by a precise and variable amount. One embodiment is directed to a high speed delay line used in automated test equipment. The inventors have recognized and appreciated that an input signal having high data rate may be split into parallel split signals having lower data rates that are delayed in respective parallel delay paths before being combined to generate a delayed signal. One advantage of delaying a signal in such a fashion is to provide high delay line timing accuracy at high data speeds, while using a compact circuit design using circuitry components of lower bandwidth with reduced power consumption, for example by using complementary metal-oxide-semiconductor (CMOS). A further advantage is that a high speed delay line may be constructed from multiple lower data rate parallel delay lines that are modular, simplifying circuit design.