Parallel Signal Delay Circuit for Phase Alignment Without Added Area

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Solution Overview

Problem

In semiconductor integrated circuits with parallel delay paths, it is challenging to maintain appropriate delay adjustments for different signal types, leading to potential phase misalignment and increased circuit size when trying to equalize delays across paths.

Innovation Solution

The semiconductor integrated circuit employs a configuration with a variable delay circuit and a duty adjustment circuit, where the delay control circuit adjusts the variable delay circuit in the strobe signal path to be smaller than in other paths, using a delay control circuit to equalize delays across multiple paths without increasing circuit size by adding dummy duty adjustment circuits.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If dummy duty adjustment circuits are added to equalize delays across parallel paths, then delay equalization is improved, but circuit size increases

Engineering Contradiction:
Improvedelay equalizationVSAvoidcircuit size
Core Design Contradiction:
Manufacturing precisionVSArea of stationary object

Solution Approach 1:

The patent applies local quality by providing the duty adjustment circuit only in the first signal transmission path where it is needed, rather than uniformly in all paths. The delay control circuit locally adjusts the delay amount in the first path to compensate for the duty adjustment delay, achieving delay equalization across paths without adding circuits to all of them.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

Instead of adding dummy duty adjustment circuits to all paths to equalize delays (the conventional approach), the patent inverts the approach by providing the duty adjustment circuit in only one path and compensating for its delay through the delay control circuit. This reverse strategy achieves the same delay equalization goal while reducing overall circuit size.

Inventive Principle:
Principle #13The other way round (Inversion)

2Measurement precision

If delay amounts are adjusted for different signal types in parallel paths, then signal transmission accuracy is improved, but device complexity increases

Engineering Contradiction:
Improvesignal transmission accuracyVSAvoiddevice complexity
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The delay control circuit serves multiple functions: it controls the variable delay circuits in each path and simultaneously compensates for the duty adjustment delay in the first path. This multi-functionality allows accurate delay adjustment for different signal types without proportionally increasing device complexity.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The patent uses parameter changes by adjusting the delay amount as a controllable variable through the delay control circuit. The delay amount in the first path is dynamically adjusted to compensate for duty adjustment effects, enabling accurate signal transmission without complex structural modifications.

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS11031928B2Semiconductor integrated circuit and transmission device
Publication Date: 2021.06.08 KIOXIA CORP
  • US11031928B2 patent drawing
  • US11031928B2 patent drawing
  • US11031928B2 patent drawing

AI summary

A semiconductor integrated circuit includes a first signal transmission path and a second signal transmission path in parallel with each other, a first variable delay circuit provided on the first signal transmission path and configured to cause a first signal to be delayed by a first delay amount, a duty adjustment circuit provided on the first signal transmission path in series with the first variable delay circuit, and a second variable delay circuit provided on the second signal transmission path and configured to cause a second signal to be delayed by a second delay amount. The first delay amount is smaller than the second delay amount by a third delay amount corresponding to an amount of delay applied to the first signal by the duty adjustment circuit.