Parallel Delta-Sigma Modulator Architecture for Lower Quantization Noise
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Solution Overview
Problem
Delta-sigma modulators used in communication devices like portable telephones and wireless LANs face challenges in achieving good noise characteristics due to high quantization noise and limited operation speed, which is not effectively addressed by existing solutions.
Innovation Solution
A digital modulator configuration that includes multiple internal delta-sigma modulators with a signal adjuster and encoder, which adjusts signal levels and encodes outputs to reduce quantization noise without decreasing operation speed, utilizing a signal adjuster with multiple output lines and level adjusters to distribute input signals across multiple delta-sigma modulators, and an encoder to combine their outputs effectively.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a single delta-sigma modulator is used to convert multi-bit signals to one-bit signals, then the device complexity is low, but the quantization noise is high and noise characteristics are poor
Solution Approach 1:
The patent divides a single high-resolution modulator into multiple lower-resolution modulators operating in parallel. Each modulator handles a portion of the input signal range, and their outputs are combined through encoding. This segmentation reduces quantization noise in each individual modulator while maintaining overall system performance, directly addressing the noise characteristics problem.
Solution Approach 2:
The patent combines the outputs of multiple parallel modulators through an encoding stage to produce the final one-bit output signal. The signal adjuster distributes the input signal to appropriate modulators based on signal level ranges, and the encoder merges their outputs coherently. This merging approach maintains low device complexity while achieving superior noise characteristics through the combined effect of multiple modulators.
2Measurement precision
If the operation clock frequency of the delta-sigma modulator is increased to reduce quantization noise, then the noise characteristics improve, but the power consumption increases
Solution Approach 1:
By segmenting the modulation function across multiple parallel modulators operating at lower clock frequencies, the patent reduces the power consumption of each individual modulator while collectively achieving the same noise reduction effect that would require a single high-frequency modulator. The total power consumption is distributed across multiple lower-power units.
Solution Approach 2:
The patent changes the operational parameters of the modulators by operating them at lower clock frequencies compared to a single high-frequency modulator. The signal adjuster dynamically assigns input signals to different modulators based on amplitude ranges, allowing each modulator to operate efficiently at optimized lower frequencies while maintaining overall system performance.
3Measurement precision
If the resolution of the quantizer is improved to reduce quantization noise, then the noise characteristics improve, but the operation speed decreases
Solution Approach 1:
The patent segments the high-resolution quantization function into multiple parallel lower-resolution quantizers. Each quantizer operates at full speed with reduced resolution requirements, and their combined output achieves the equivalent noise performance of a single high-resolution quantizer. This segmentation removes the speed penalty associated with high-resolution quantization.
Solution Approach 2:
The patent transitions from a single-dimension approach (one high-resolution quantizer) to a multi-dimensional parallel architecture. By distributing the quantization function across multiple dimensions (parallel channels), each operating at lower resolution but higher speed, the system achieves both improved noise characteristics and maintained operation speed through spatial parallelism.
Data Source
AI summary
To provide a digital modulator including: a signal adjuster (105) which is provided with a plurality of output lines, and which outputs, to the output line, which corresponds to a range to which a level of an input signal belongs, a signal of a level corresponding to the level of the input signal; a plurality of internal digital modulators (111-1 to 111-N), each of which is provided so as to correspond to each of the plurality of output lines and carries out delta-sigma modulation on the signal of the corresponding output line to output the modulated signal; and an encoder (113) which encodes the plurality of modulated signals respectively outputted by the plurality of internal digital modulators.