Parallel Delta-Sigma RF Amplifier for Lower Clock Rates
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Solution Overview
Problem
Delta-sigma amplifiers face challenges in generating high-speed delta-sigma modulation signals required for efficient RF amplification in LTE systems, as the modulation signal frequency must be at least twice the carrier frequency, leading to impractically high operational rates for cellular signals above 1 GHz.
Innovation Solution
The implementation of a modulator circuit with multiple signal processing branches that split and process input data streams using concatenated independent blocks, allowing each branch to operate at a lower delta-sigma bitstream rate, effectively reducing the overall clock rate and enabling efficient amplification by combining modulated signals with a window function.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If a single delta-sigma modulator is used to generate the modulation signal at the required high frequency, then the amplification efficiency can be maximized, but the operational clock rate becomes impractically high and difficult to implement
Solution Approach 1:
The patent divides a single high-speed delta-sigma modulator into multiple parallel lower-speed modulators. Each modulator operates at a reduced clock rate (e.g., 1/4th of the required output rate), and their outputs are combined through parallel signal paths to achieve the final high-frequency modulated signal. This segmentation allows efficient amplification while avoiding impractically high individual clock rates.
2Measurement precision
If the delta-sigma modulation signal frequency is set to at least twice the carrier frequency to satisfy the Nyquist theorem, then accurate signal reconstruction is achieved, but the operational rate becomes impractically high for cellular signals above 1 GHz
Solution Approach 1:
The patent applies segmentation by using multiple parallel delta-sigma modulators, each operating at a lower frequency (e.g., 1/4th of the Nyquist rate). The parallel outputs are combined to reconstruct the high-frequency signal accurately. This maintains signal reconstruction precision while making the implementation feasible with practical clock rates.
Solution Approach 2:
The patent transitions from a single-dimensional high-speed modulator to a multi-dimensional parallel architecture. By distributing the modulation task across multiple parallel paths operating at lower speeds, the system achieves the required high-frequency output through spatial parallelism rather than temporal speed, making implementation practical.
3Speed
If multiple parallel signal processing branches are used to reduce the clock rate, then the operational speed becomes practical, but the device complexity increases
Solution Approach 1:
The patent segments the modulation function into multiple parallel branches, each handling a portion of the signal at reduced speed. While this increases component count, each branch uses simplified logic operating at feasible clock rates, and the parallel structure allows modular implementation that manages overall system complexity.
Data Source
AI summary
A modulator circuit includes a plurality of signal processing branches, each branch having a modulator for performing a delta-sigma modulation of a respective data stream portion in order to generate a modulated signal. The modulator circuit receives an input data stream having a carrier frequency; splits the input data stream into a plurality of data stream portions. Delta-sigma modulation is performed in each branch on a respective data stream portion. The respective modulated signals from each branch are combined to form an output signal for outputting at the carrier frequency.