Parallel Design Technology Optimization SPICE Model Co-Verification
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Solution Overview
Problem
The conventional design and technology interaction systems face challenges such as slow model turnaround times, separation of manufacturing technology and circuit design process loops, and difficulties in understanding and adjusting model parameters, making co-optimization of technology process and design process impractical.
Innovation Solution
A method and system for parallel design and technology optimization (PDTO) that generates a baseline SPICE model from manufacturing technology, extends it to a technology specification window in the circuit design process, and extracts a targeted SPICE model to verify the integrated circuit meets design specifications, allowing for simultaneous optimization of both processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional SPICE simulation methods are used for whole system simulation, then accurate predictions of circuit behavior are achieved, but simulation time becomes excessively long and computational complexity increases beyond practical limits
Solution Approach 1:
The patent divides the circuit into hierarchical levels: device level, cell level, and system level. Each level has its own optimized simulation approach, allowing accurate device-level simulations to be performed separately while using aggregated models at higher levels, thus reducing overall simulation time without sacrificing accuracy where needed
Solution Approach 2:
The patent introduces a new dimension of abstraction by creating intermediate cell-level models that aggregate device behavior. This hierarchical dimensionality allows the simulation to skip detailed device-level computations at the system level while maintaining accuracy through properly constructed intermediate models, effectively solving the time-accuracy tradeoff
2Manufacturing precision
If detailed device-level simulation is performed for the entire circuit, then nanometer effects are accurately captured, but computational resources and simulation time become prohibitive
Solution Approach 1:
The patent applies local quality by performing detailed device-level simulations only in specific regions or circuits where nanometer effects are critical, while using aggregated models in regions where such detailed analysis is not necessary. This localized approach maintains manufacturing precision where needed while reducing overall computational complexity
3Ease of manufacture
If technology process and circuit design are optimized separately in sequential loops, then each process can be optimized independently, but co-optimization opportunities are lost and development cycle time increases
Solution Approach 1:
The patent merges the technology process optimization loop and circuit design optimization loop into a unified co-optimization framework. By integrating device modeling, circuit simulation, and technology specification development into a single systematic approach, the patent enables simultaneous optimization of both processes while capturing synergistic effects that sequential optimization would miss
4Ease of operation
If conventional sequential optimization processes are used, then model development can be completed with simpler procedures, but model turnaround time becomes excessively long
Solution Approach 1:
The patent applies preliminary action by pre-characterizing devices and pre-defining cell-level models during the technology development phase. These pre-computed models and parameters are then reused across multiple circuit designs, eliminating the need to perform detailed device simulations repeatedly and significantly reducing model turnaround time while maintaining ease of operation through standardized interfaces
Data Source
AI summary
Method and System for Parallel Design and Technology Optimization are disclosed. The disclosed method enables efficient parallel design and technology optimization (PDTO) and allow designers to sign off the technology development or find the optimal design point with the design analysis tools. The method includes generating, from a manufacturing technology process, a baseline SPICE model based on technology specification and manufacturing process data; extending the baseline SPICE model to a corresponding description of technology specification window in the circuit design process, where the technology specification window describes extended ranges of device model parameters; extracting a targeted SPICE model using the technology specification window; verifying, by a circuit design process that operates in parallel to the manufacturing technology process, the integrated circuit meets a design specification using the targeted SPICE model.