Parallel DFE Filter Loops for Higher Data Rates With Low Complexity
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Solution Overview
Problem
Current Decision Feedback Equalizer (DFE) filters are limited by their operating frequency range and complexity, which increases with data rate, making it difficult to achieve high data rates without increasing component count or cost.
Innovation Solution
A DFE filter architecture with two parallel filter loops, each comprising a summer, latch circuits, delay circuits, linear buffers, limiting amplifiers, automatic gain control, and de-multiplexer, allowing for half-rate sampling and parallel processing to extend the data-rate capability while maintaining low complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a single DFE filter loop is used, then the component count is low, but the operating frequency range is limited and cannot achieve high data rates
Solution Approach 1:
The DFE filter is segmented into two parallel filter loops (first and second filter loops) that operate simultaneously. Each loop processes different portions of the data stream, allowing the overall system to achieve higher data rates by dividing the processing workload across multiple parallel paths rather than increasing the complexity of a single sequential path.
2Productivity
If the data rate is increased in a conventional DFE filter, then higher throughput is achieved, but the settling time increases causing timing jitter sensitivity
Solution Approach 1:
The first latch circuit in each filter loop performs preliminary sampling and holding of the input signal before the main decision circuit processes it. This preliminary action allows the settling transition to be hidden from the decision circuit, effectively reducing the sensitive settling time and making the system less sensitive to timing jitter even at high data rates.
3Speed
If parallel processing is implemented to increase data rate, then throughput improves, but the device complexity and cost increase
Solution Approach 1:
The two filter loops are merged in a parallel architecture where they share common components and processing stages. The first and second filter loops are substantially identical and operate in parallel, with their outputs combined through the de-multiplexer and automatic gain control circuit, achieving frequency multiplication while maintaining a compact and efficient structure that avoids duplicating the entire system.
Data Source
AI summary
A DFE filter includes an input, a first filter loop coupled to the input for providing an odd bit-stream, and a second filter loop coupled to the input for providing an even bit-stream, wherein the first and second filter loops are identical and interleaved.