Parallel Decision Feedback Equalizer for High-Speed Serial Links
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
High-speed digital communications face significant distortion and intersymbol interference due to inadequate frequency response in serial links, making it difficult for existing decision feedback equalizers (DFEs) to handle high bit rates without requiring a clock frequency equal to or greater than the bit rate, limiting their implementation at high speeds.
Innovation Solution
A parallel processing arrangement using two or more decision feedback equalizers (DFEs) operating concurrently, each processing alternating bits and compensating for distortion without waiting for preceding bit determinations, allowing for effective compensation of high bit rate signals at a clock rate half that of the input signal, thereby reducing hardware requirements and roundoff errors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a single decision feedback equalizer processes all bits sequentially, then the clock frequency must be equal to or greater than the bit rate, but this increases hardware complexity and makes high-speed implementation difficult
Solution Approach 1:
The patent divides the bit stream into two separate sequences (even-positioned bits and odd-positioned bits) and processes them through two parallel DFE pipelines. This segmentation allows each pipeline to operate at half the bit rate, reducing the clock frequency requirement from ≥bit rate to ≥bit rate/2, thereby reducing hardware complexity while maintaining high-speed capability
Solution Approach 2:
The patent transforms the sequential single-pipeline architecture into a parallel multi-pipeline architecture by adding a dimension of concurrency. Two DFE pipelines operate simultaneously on different bit sequences, effectively doubling the processing throughput without requiring each pipeline to run at full bit rate, thus reducing hardware complexity requirements
2Measurement precision
If the clock frequency is increased to match the bit rate for accurate processing, then processing accuracy improves, but power consumption and hardware resource requirements increase
Solution Approach 1:
By segmenting the bit stream into even and odd sequences processed by separate pipelines, each pipeline operates at half the bit rate. This reduces the clock frequency requirement from ≥bit rate to ≥bit rate/2, thereby reducing power consumption while maintaining processing accuracy through parallel concurrent operation of both pipelines
3Measurement precision
If more preceding bits are used in the feedback loop, then the accuracy of distortion compensation increases, but the device complexity and processing time increase
Solution Approach 1:
The patent applies segmentation to the feedback processing by creating separate feedback loops for even and odd bit sequences. Each pipeline maintains its own feedback register storing compensation values for its specific sequence, allowing accurate multi-bit history compensation within each pipeline at reduced complexity compared to a single comprehensive feedback system
Data Source
AI summary
An integrated circuit includes a decision feedback equalizer (DFE) including a first and second digital equalizer logic including circuitry to compensate first and second bits in a received stream and to provide first and second sign bits. The second equalizer logic can run concurrently and can be connected in parallel relative to the first equalizer logic. The second equalizer logic can include a low and high sign bit pipelines providing first and second conditional sign bits by assuming a low and high sign bits, respectively, for a first bits being concurrently processed by the first equalizer logic and a sign bit selection element to select between the first and second conditional sign bits based on the sign bit outcome of the first equalizer logic. The first and second pipelines compensate bits using compensation weights chosen using most recent first and second conditional sign bits and sign bit outcome.