Parallel Decision Feedback Equalizer for Low-Complexity ISI Cancellation
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Solution Overview
Problem
In high-speed data communication systems, traditional digital signal processing (DSP) implementations of Decision Feedback Equalizers (DFE) face challenges due to their complex feedback structure, leading to prohibitively large designs and high power consumption, while analog equalizers have limitations in improving data eye margin effectively.
Innovation Solution
A parallel DFE architecture is introduced, featuring an analog-to-digital converter, a parallelizer, and multiple decision feedback equalizers with shared tap weight coefficients, which processes digitized symbols in parallel, reducing clock frequency requirements and hardware complexity, and utilizing prefix buffers to improve processing continuity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a traditional DFE is implemented with multiple taps to cancel ISI, then the ISI cancellation performance improves, but the hardware complexity and power consumption increase exponentially
Solution Approach 1:
The patent divides the single complex DFE into multiple parallel DFE instances, each handling a subset of the equalization task. Specifically, it uses multiple DFEs with fewer taps each, operating in parallel to achieve the same overall ISI cancellation as a single DFE with many taps, thereby reducing individual filter complexity while maintaining performance
Solution Approach 2:
The patent transitions from a serial processing architecture to a parallel processing architecture by adding the dimension of time-multiplexed parallel operation. Multiple DFEs process different symbol periods in parallel, effectively distributing the computational load and reducing the complexity of each individual DFE unit
2Measurement precision
If the number of DFE taps is increased to cancel more ISI terms, then the equalization accuracy improves, but the power consumption increases
Solution Approach 1:
The patent segments the total equalization function across multiple DFE units, each with reduced tap counts. This distribution allows the system to achieve high equalization accuracy through collective processing while each individual unit consumes less power, resulting in overall reduced power consumption compared to a single high-complexity DFE
Solution Approach 2:
Each individual DFE in the parallel configuration performs partial equalization (handling only a portion of the ISI cancellation), but the collective action of all parallel DFEs provides the complete or excessive equalization needed, achieving high accuracy without requiring each unit to be fully capable alone
3Speed
If a fully unrolled DFE is implemented for parallel processing, then the clock speed requirements are reduced, but the design size scales exponentially and becomes prohibitively large
Solution Approach 1:
The patent applies segmentation by dividing the unrolled DFE structure into multiple manageable parallel units. Instead of implementing one large unrolled DFE that scales exponentially, it creates several smaller unrolled DFEs that can be implemented with reasonable area, each handling a portion of the parallel processing task
Solution Approach 2:
The patent resolves the area-speed tradeoff by introducing parallel time-multiplexed processing. Multiple reduced-complexity DFEs operate in parallel across different time slots, achieving the same effective processing rate as a large unrolled DFE would provide sequentially, but with much smaller total area
Data Source
AI summary
Described embodiments apply equalization to an input signal to a receiver such as a serial-deserializer. The receiver has an analog-to-digital converter (ADC), an M-way parallelizer, N serial buffers, N prefix buffers, and N decision feedback equalizers (DFEs), where M and N are greater than one. The ADC digitizes the input signal to form digitized symbols. The parallelizer assembles the digitized symbols into parallel sets of M digitized symbols. Each serial buffer has slots of M locations per slot and stores one set of M digitized symbols in one of the slots. The DFEs are responsive to common tap weight coefficients and produce parallel sets of M recovered data bits. Each DFE is first trained using sets of past digitized symbols loaded into a corresponding one of the prefix buffers and then processes digitized symbols stored in a corresponding one of the serial buffers.