Parallel Decision Feedback Equalizer for High Throughput
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Solution Overview
Problem
Existing communication systems face challenges in achieving high-throughput, low-complexity decision feedback equalization, particularly in channels with nonlinear distortions, where traditional equalizers struggle to process multiple symbols in parallel without violating timing constraints.
Innovation Solution
A parallel Decision Feedback Equalizer (DFE) architecture that divides processing into sub-tasks, using multiple processing blocks with lookahead modules and selection logic to produce lookahead values, which meet timing constraints by employing Feed Forward and Feed Back filters, including Lookup Tables for efficient filtering and adaptive updates.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If traditional equalizers process multiple symbols in parallel, then throughput increases, but timing constraints are violated
Solution Approach 1:
The patent divides the processing of N symbols into multiple processing blocks, where each block handles a subset of symbols (N′ < N). This segmentation allows the chained calculation to be performed in smaller steps that meet timing constraints, while still achieving high throughput through parallel processing of multiple blocks. The selection logic then combines results from different blocks to produce the final output.
2Productivity
If parallel processing is implemented to increase throughput, then productivity improves, but device complexity increases
Solution Approach 1:
By segmenting the parallel processing into multiple processing blocks that each handle fewer symbols, the patent reduces the complexity of individual blocks while maintaining overall throughput. Each block contains a manageable number of lookahead modules, making the design more implementable and easier to optimize.
Solution Approach 2:
The patent employs preliminary speculative decoding in lookahead modules that generate candidate values before the final decision is made. This preliminary action allows the system to prepare multiple potential outcomes in parallel, reducing the critical path complexity of the main processing chain while maintaining high throughput.
3Productivity
If more lookahead modules are added to process more symbols, then throughput increases, but power consumption increases
Solution Approach 1:
The patent segments the lookahead modules into multiple processing blocks, where each block handles a subset of symbols. This segmentation reduces the power consumption of individual blocks while maintaining overall throughput through parallel operation. The selection logic efficiently combines results from blocks, activating only the necessary computational paths.
Data Source
AI summary
In some disclosed embodiments, a Decision Feedback Equalizer (DFE) processes multiple symbols in parallel using a novel architecture that avoids violating a timing constraint. The DFE comprises Feed-Back (FB) filters that can be configured to equalizing nonlinear phenomena. Using a Look-Up Table (LUT)-based implementation, the FB filters may implement complex nonlinear functions at low hardware complexity, low latency and low power consumption. A LUT-based implementation of the FB filter supports adaptive FB filtering to changing channel conditions by updating LUT content.