Parallel Decision Feedback Equalizer for 10 Gb/s Optical Links

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Solution Overview

Problem

Conventional decision feedback equalizers face challenges in generating error signals quickly enough to compensate for intersymbol interference at high data rates, such as 10 Gbit/s, due to the short symbol interval of 100 picoseconds, which is unachievable with current silicon semiconductor processing technologies.

Innovation Solution

The implementation of high-speed decision feedback equalization using parallelization and pre-computation techniques, including a pre-computation unit that samples signals, compares them to thresholds, selects speculative decisions, and updates counters to adjust thresholds, allowing for extended feedback computation time and improved reliability in optical transceiver modules.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If conventional cascaded circuit elements are used to generate error signals in a decision feedback equalizer, then the equalization function can be implemented, but the computation cannot be completed within the short symbol interval at 10 Gbit/s

Engineering Contradiction:
Improvedata transmission rateVSAvoidcomputation time
Core Design Contradiction:
ProductivityVSLoss of time

Solution Approach 1:

The patent applies pre-computation by calculating feedback coefficients in advance during training sequences before actual data transmission occurs. The equalizer computes and stores these coefficients beforehand, so that during normal operation at 10 Gbit/s, no real-time computation is needed - the pre-computed coefficients are simply applied to incoming signals, eliminating the time constraint problem.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent replaces the traditional real-time cascaded circuit computation approach with a different mechanism: using pre-computed feedback coefficients stored in memory. Instead of performing complex circuit computations within the symbol interval, the system substitutes this with simple look-up and multiplication operations using pre-calculated values, thereby achieving high-speed operation.

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

2Productivity

If the symbol rate is increased to achieve higher data transmission rates, then productivity improves, but the symbol interval becomes too short for conventional equalization circuits to operate correctly

Engineering Contradiction:
Improvedata transmission rateVSAvoidsymbol interval
Core Design Contradiction:
ProductivityVSDuration of action of moving object

Solution Approach 1:

The patent uses training sequences transmitted at lower rates to pre-compute feedback coefficients before high-speed data transmission begins. This preliminary action during training allows the system to be configured for high-speed operation without requiring real-time computation during the actual high-rate data transmission, resolving the contradiction between high productivity and short symbol interval.

Inventive Principle:
Principle #10Preliminary action

3Reliability

If decision feedback equalization is implemented to reduce intersymbol interference, then signal quality improves, but the complexity of the equalization circuit increases

Engineering Contradiction:
Improvedata recovery accuracyVSAvoidequalization circuit complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent simplifies the equalization circuit by pre-computing all necessary feedback coefficients during training sequences. During normal high-speed operation, the circuit only needs to store and apply these pre-computed coefficients rather than performing complex real-time computations. This reduces the operational complexity of the circuit while maintaining high reliability in data recovery.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS20110116806A1High-Speed Adaptive Decision Feedback Equalizer
Publication Date: 2011.05.19 CREDO TECHNOLOGY GROUP LTD
  • US20110116806A1 patent drawing
  • US20110116806A1 patent drawing
  • US20110116806A1 patent drawing

AI summary

A decision-feedback equalizer (DFE) can be operated at higher frequencies when parallelization and pre-computation techniques are employed. Disclosed herein is a DFE design that operates at frequencies above 10 GHz, making it feasible to employ decision feedback equalization in optical transceiver modules. An adaptation technique is also disclosed to maximize communications reliability. The adaptation module can be treated as a straightforward extension of the pre-computation unit. At least some method embodiments include, in each time interval: sampling a signal that is partially compensated by a feedback signal; comparing the sampled signal to a set of thresholds to determine multiple speculative decisions; selecting and outputting one of the speculative decisions based on preceding decisions; and updating a counter if the sampled signal falls within a window proximate to a given threshold. Once a predetermined interval has elapsed, the value accumulated by the counter is used to adjust the given threshold.