Parallel DFE Receiver Circuit for High-Baud PAM Signaling
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Solution Overview
Problem
Existing receiver circuits for pulse amplitude modulation (PAM) signaling face challenges in processing high baud rates due to timing critical paths, particularly in decision feedback equalizer (DFE) circuits, which limit the frequency of signal processing.
Innovation Solution
The proposed receiver circuit employs a plurality of decision feedback equalizer sub-circuits, each clocked by a different divided clock signal, with a first and second delay block and a slicer, operating at a fraction of the network frequency, and utilizes speculative circuits for generating output symbols, reducing the timing critical path.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a single decision feedback equalizer circuit is used for PAM signal processing, then the circuit structure is simple, but the processing frequency is limited due to timing critical paths
Solution Approach 1:
The patent divides the single decision feedback equalizer circuit into multiple parallel sub-circuits (first decision feedback equalizer sub-circuit, second decision feedback equalizer sub-circuit, etc.), each operating at a lower frequency with its own clock signal. This segmentation allows each sub-circuit to process signals without creating critical timing paths, thereby increasing the overall processing frequency while maintaining manageable circuit complexity through modular architecture.
2Productivity
If multiple decision feedback equalizer sub-circuits are used to increase processing frequency, then the signal processing frequency improves, but the device complexity increases
Solution Approach 1:
The patent combines multiple decision feedback equalizer sub-circuits that operate in parallel, each clocked by divided clock signals. The outputs of these sub-circuits are merged through a switching circuit to produce the final output symbol stream. This merging approach allows the system to achieve higher baud rates by processing signals simultaneously through multiple sub-circuits while managing complexity through standardized modular units.
Solution Approach 2:
The patent employs dynamic clocking mechanisms where multiple clock signals are divided into different phases, and the switching circuit dynamically selects which sub-circuit output to present at the output terminal. This dynamic operation allows flexible scheduling of processing operations across multiple sub-circuits, optimizing throughput while managing resource allocation to control overall system complexity.
3Loss of time
If speculative circuits are added to generate output symbols, then the timing critical path is reduced, but the circuit complexity increases
Solution Approach 1:
The patent incorporates speculative circuits that perform preliminary actions by generating multiple possible output symbol values in advance based on different assumed previous symbol values. These speculative outputs are prepared beforehand and then selected based on the actual previous symbol detected by the decision feedback mechanism. This preliminary computation reduces the timing critical path by eliminating sequential dependency delays while adding complexity only through the speculative generation and selection logic.
Data Source
AI summary
A receiver circuit that includes decision feedback equalizer sub-circuits, each associated with one of multiple divided clock signals. Each decision feedback equalizer sub-circuit is configured to receive Pulse Amplitude Modulation (PAM) signalling that represents a current network symbol. Each of the decision feedback equalizer sub-circuits is configured for sequential generation of an output symbol and includes a first delay block that is configured to apply a delay to the PAM signalling in order to provide delayed PAM signalling, where the first delay block is clocked by a divided clock signal that is associated with the decision feedback equalizer sub-circuit, a coefficient application block, a slicer, and a second delay block that is configured to apply a delay to a DFE-sub-circuit output symbol from the slicer in order to provide an output symbol, wherein the second delay block is clocked by the divided clock signal.