Parallel DFP-to-BCD Conversion in Floating Point Units
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Solution Overview
Problem
Current decimal floating point (DFP) to binary coded decimal (BCD) conversion methods are inefficient, requiring multiple cycles due to sequential execution of rounding and conversion loops, which hampers the high-frequency operations of modern microprocessors.
Innovation Solution
Implementing parallel execution of rounding and conversion loops within the floating point unit of a processor, allowing the conversion loop to start subsequent to the rounding loop, thereby reducing the number of cycles required for converting DFP numbers to BCD numbers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If sequential execution of rounding and conversion loops is used, then conversion accuracy is maintained, but conversion time increases requiring multiple cycles
Solution Approach 1:
The rounding loop is executed first to determine the rounding mode and calculate rounding information before the conversion loop begins. This preliminary action allows the conversion loop to use pre-calculated rounding values, enabling both operations to proceed efficiently with accurate results.
Solution Approach 2:
The patent implements overlapping execution where the conversion loop starts after the rounding loop begins, and both loops run in parallel. This continuous execution eliminates idle waiting time between operations while maintaining the required sequence for accuracy, thus reducing total conversion cycles.
2Productivity
If parallel execution of rounding and conversion loops is implemented, then conversion speed increases reducing cycles needed, but pipeline complexity increases
Solution Approach 1:
The conversion process is divided into two independent loops: a rounding loop that calculates rounding information, and a conversion loop that performs the actual DFP to BCD conversion. These segmented loops can execute in parallel with minimal interaction, reducing overall execution time while keeping each loop's logic simple and manageable.
Solution Approach 2:
The patent introduces an intermediary mechanism where rounding information is calculated first and then passed to the conversion loop. This intermediary data structure allows the two loops to operate independently in parallel while maintaining their functional relationship, simplifying the pipeline control logic.
3Power
If multiple pipeline stages are used to support high frequencies, then processing capability increases, but conversion efficiency decreases due to sequential loop execution
Solution Approach 1:
The patent implements dynamic pipeline scheduling where the conversion loop is launched at a specific point during the rounding loop execution rather than waiting for completion. This dynamic approach allows multiple pipeline stages to be utilized effectively, maintaining high processing capability while improving conversion efficiency through overlapping execution.
Data Source
AI summary
A computer-implemented method includes: receiving, using a processor, a decimal floating point number; and using a floating point unit within the processor to convert the decimal floating point number into a binary coded decimal number, wherein the floating point unit starts a conversion loop subsequent to a rounding loop starting, wherein the rounding loop and the conversion loop run in parallel once started.