Parallel Digital PLL Chains for Continuous High-Speed Phase Tracking
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Solution Overview
Problem
Conventional phase-locked loops (PLLs) in high-speed digital receivers face challenges in continuous error calculation and tracking, leading to discontinuous sequential inputs when multiple parallel PLL units are used, which affects performance in applications like 10 Gb/s or higher rate digital receivers.
Innovation Solution
A parallel PLL system with two chains of PLLs, where the first chain operates from a free-run state to a locked state and the second chain processes signal output from the locked state, allowing for segment-by-segment parallel processing and enabling high-speed throughput by initializing internal states and using decision-directed PLLs with voltage-controlled oscillators for phase rotation and error calculation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple parallel PLL units are used for high-speed processing, then processing throughput is improved, but input continuity deteriorates causing sequential discontinuities
Solution Approach 1:
The patent divides the continuous input signal into discrete segments and assigns each segment to a different PLL unit for parallel processing. This segmentation enables multiple PLLs to operate simultaneously on different data portions, achieving high throughput while maintaining logical continuity through proper state management between segments.
Solution Approach 2:
The patent implements preliminary initialization of PLL internal states before parallel processing begins. By pre-configuring the starting conditions for each PLL unit, the system ensures that when segments are processed in parallel, the continuity of phase and frequency tracking is maintained without requiring sequential operation.
2Measurement precision
If conventional PLL is used for continuous error calculation, then phase tracking accuracy is improved, but processing speed deteriorates in high-speed applications
Solution Approach 1:
The patent transforms the continuous error calculation of conventional PLL into periodic discrete error calculations suitable for parallel processing. By calculating phase errors at specific intervals corresponding to segment boundaries rather than continuously, the system maintains tracking accuracy while enabling high-speed parallel operation across multiple PLL units.
Solution Approach 2:
The patent replaces the mechanical continuous feedback mechanism of conventional PLL with a digital parallel processing approach. Instead of continuous analog-like error calculation, the system uses discrete digital error calculations performed simultaneously by multiple PLL units, achieving both high speed and accuracy through parallel computation.
3Productivity
If parallel PLL units operate independently, then processing throughput is improved, but phase coherence deteriorates
Solution Approach 1:
The patent implements feedback mechanisms where the output state of one PLL unit is used to initialize or adjust the input state of the next PLL unit in the sequence. This feedback loop ensures that phase coherence is maintained across all parallel PLL units, allowing them to operate independently for high throughput while remaining synchronized in their phase tracking.
Solution Approach 2:
The patent uses intermediate state variables as mediators between parallel PLL units. These intermediate states carry phase and frequency information from one PLL unit to the next, ensuring that all units maintain coherent phase relationships while processing different segments in parallel, thus preserving reliability across the distributed system.
Data Source
AI summary
A parallel phase locked loop (PLL) system includes a first chain of a plurality of pre-locking PLLs that operates from a free-run state to a locked state; and a second chain of a plurality of PLLs to work from the locked-state to recover signal output.