Parallel Domain Crossing Circuits for High-Speed Data Transmission
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Solution Overview
Problem
Existing methods for data transmission between asynchronous circuits with different voltages and clock speeds are unreliable and not scalable, especially at high frequencies, leading to timing errors and increased design complexity as die size increases.
Innovation Solution
A method and apparatus that utilize multiple domain crossing circuits operating in parallel, with data transmitted through multiple electrical paths, allowing each circuit to operate every second cycle, and using a round robin fashion as frequency increases, to maintain reliable data transmission across domains with differing voltage and clock frequencies.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If synchronous circuits operate on the same clock speed and voltage, then reliability is readily achieved, but power consumption increases and flexibility is reduced
Solution Approach 1:
The patent applies dynamics by enabling circuits to switch between synchronous and asynchronous operation modes. The system dynamically adjusts the clocking mechanism based on operational requirements, allowing circuits to operate asynchronously when power saving is needed and synchronously when reliability is paramount. This dynamic adaptability resolves the contradiction between reliability and power consumption.
Solution Approach 2:
The patent changes the operational parameters of the circuit by introducing asynchronous FIFO memory and level shifters that enable voltage and clock frequency transitions. The system can operate at different voltage levels (e.g., 1.8V to 3.3V) and clock frequencies without requiring synchronous operation, thereby reducing power consumption while maintaining reliability through proper domain crossing protocols.
2Adaptability or versatility
If asynchronous FIFO memory and level shifters are inserted in the data path, then asynchronicity between domains is accommodated, but device complexity increases
Solution Approach 1:
The patent extracts the clocking and synchronization logic from the main data path by using asynchronous FIFO memory. The read and write pointers are separated into different clock domains, with the FIFO buffer absorbing the timing differences. This extraction reduces the complexity of coordinating multiple synchronous circuits across voltage domains.
Solution Approach 2:
The asynchronous FIFO memory acts as an intermediary buffer between circuits operating at different voltages and clock frequencies. The level shifter serves as another intermediary that mediates voltage level transitions. These intermediary components simplify the overall system by isolating the asynchronous domains from direct interaction.
3Adaptability or versatility
If data traverses through level shifter twice and passes through read multiplexer logic, then voltage domain crossing is achieved, but timing requirements cannot be met at high frequencies
Solution Approach 1:
The patent segments the data transmission path into multiple independent stages using parallel domain crossing circuits. Each circuit handles a portion of the data width, allowing data to be transmitted through multiple smaller, faster paths rather than a single bottleneck path. This segmentation enables high-frequency operation by distributing the timing requirements across multiple parallel channels.
Solution Approach 2:
The patent transitions from a single-dimensional sequential data path to a multi-dimensional parallel architecture. By using multiple domain crossing circuits operating in parallel and selecting from multiple electrical paths, the system adds a spatial dimension to data transmission. This dimensional change allows simultaneous data flow through multiple paths, achieving high-speed transmission at 1 GHz and beyond.
4Reliability
If synchronous operation is enforced between domains, then data transfer reliability is maintained, but design tolerances become more taxing and scalability is reduced
Solution Approach 1:
The patent applies dynamics by allowing the system to operate in asynchronous mode with proper domain crossing protocols, eliminating the need for strict synchronous timing. The asynchronous FIFO and handshaking mechanisms dynamically manage data transfer between domains without requiring matched clock frequencies or phase alignment, thereby reducing design tolerance requirements while maintaining reliability.
Solution Approach 2:
The patent changes the operational parameters by accepting asynchronous operation with varying clock frequencies and voltage levels between domains. The level shifters and FIFO memory accommodate parameter variations without requiring tight synchronization, making the system more scalable and less sensitive to process, voltage, and temperature variations.
Data Source
AI summary
A method and system is provided for allowing signals across electrical domains. The method includes applying a clock signal (of at least 1 GHz) to an electronic element in a location having first electrical properties. Data is output from the first electronic element; and received at a second electronic element located in a location having second electrical properties. The first and second electrical properties are different by either voltage and clock frequency.