Parallel Digital Predistortion Feedback for Ultra-Wideband ADC Limits
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Solution Overview
Problem
The energy consumption of analog-to-digital converters (ADCs) in digital predistortion processing systems cannot meet the requirements of ultra-large bandwidths, such as those needed for future 5G mobile communications technologies, which demand higher bandwidths than previous systems can efficiently handle.
Innovation Solution
A digital predistortion processing apparatus is designed with multiple digital predistortion elements and an analog-to-digital conversion unit that performs signal extraction at a lower rate, allowing for efficient processing and feedback without increasing the technical level of existing components like FPGA and ADC, thereby reducing energy consumption and implementation costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If a high-speed ADC is used to sample feedback signals with bandwidth four to five times larger than signal bandwidth, then the bandwidth requirement is met, but energy consumption becomes excessive for ultra-large bandwidth applications
Solution Approach 1:
The patent divides the feedback signal processing into multiple parallel channels, each handling a portion of the total bandwidth. Instead of using one high-speed ADC to process the entire ultra-wideband feedback signal, the system segments the signal into multiple narrower bandwidth streams that can be processed by lower-speed ADCs, thereby reducing energy consumption while maintaining overall bandwidth capability
Solution Approach 2:
The patent introduces a time-domain dimension by using multiple ADCs operating at different time instances or with different sampling rates to collectively capture the ultra-wideband feedback signal. This dimensional approach allows the system to achieve high effective bandwidth through temporal multiplexing rather than requiring a single high-speed converter, thus reducing power consumption
2Area of stationary object
If 2-fold bandwidth sampling is used to handle larger bandwidth, then bandwidth requirement is satisfied, but device complexity increases due to multiple processing stages
Solution Approach 1:
The patent merges multiple parallel processing channels into a unified feedback loop architecture. By combining the outputs of multiple digital predistortion elements that process segmented signal portions, the system achieves high-bandwidth predistortion correction without requiring complex sequential processing stages, thus reducing overall device complexity while maintaining bandwidth performance
3Ease of manufacture
If existing ADC and FPGA components are used without upgrading, then implementation cost is reduced, but energy consumption cannot meet ultra-large bandwidth requirements
Solution Approach 1:
The patent segments the ultra-wideband signal processing task across multiple existing ADC and FPGA components, allowing the system to achieve ultra-large effective bandwidth by parallelizing processing across available lower-speed components. This approach enables cost-effective implementation without requiring expensive upgraded hardware, while the segmented architecture distributes energy consumption across multiple components rather than overloading a single component
Data Source
AI summary
Embodiments of the present disclosure provide a digital predistortion processing apparatus, where the apparatus includes an analog-to-digital conversion unit and n digital predistortion elements. The analog-to-digital conversion unit is connected to the n digital predistortion elements. Each digital predistortion element is configured to receive n input signals, perform digital predistortion processing on the n input signals, and then output n processed signals. The analog-to-digital conversion unit is configured to receive the n processed signals, perform signal extraction based on the n processed signals, and output an extracted signal, where a rate of the extracted signal is the same as a rate of each of the n processed signals. For an ultra-large-bandwidth signal, DPD correction may be performed without increasing a technical level of existing components such as an FPGA and an ADC, thereby greatly reducing implementation costs.