Parallel Duty Correction Circuit for Multi-Chip Nonvolatile Memory
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Solution Overview
Problem
Conventional nonvolatile memory devices face performance degradation due to duty mismatch in clock signals, leading to reduced effective data windows and increased latency, especially when communicating at lower frequencies with controllers.
Innovation Solution
Incorporating a duty correction circuit (DCC) in each memory chip that performs parallel duty correction operations during a dedicated training period, using external clock signals to generate corrected internal clock signals, and employing output buffers to transmit these corrections to input/output pins, thereby maintaining consistent performance even with multiple memory chips.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If duty correction operation is performed sequentially in multiple memory chips, then each chip can be corrected properly, but the total correction time increases significantly
Solution Approach 1:
The patent divides the duty correction operation into independent segments that can be executed simultaneously across multiple memory chips. Each chip performs its own duty correction operation independently based on the same external clock signal, allowing parallel processing without interference between chips.
Solution Approach 2:
The patent merges the duty correction operations of multiple memory chips into a single parallel execution phase. By coordinating all chips to perform duty correction simultaneously during the training period, the system achieves both individual chip accuracy and overall time efficiency.
2Quantity of substance
If multiple memory chips are used to increase storage capacity, then system capacity improves, but maintaining consistent performance across all chips becomes more difficult
Solution Approach 1:
The patent implements a universal duty correction mechanism that all memory chips share. Each chip contains an identical duty correction circuit structure that operates according to the same external clock signal, ensuring consistent performance characteristics across all chips regardless of quantity.
Solution Approach 2:
The patent adjusts the duty cycle parameter of internal clock signals in each memory chip to match the external clock signal characteristics. By dynamically changing the duty cycle parameter based on the external clock signal, all chips maintain consistent timing and performance regardless of the total number of chips in the system.
3Speed
If duty correction is performed at high operating frequency, then data transmission speed improves, but duty mismatch errors increase
Solution Approach 1:
The patent performs duty correction as a preliminary action during a dedicated training period before normal high-speed data transmission begins. By correcting duty mismatches in advance at lower frequencies, the system prepares accurate timing references that enable reliable high-speed operation without duty cycle errors.
Solution Approach 2:
The patent implements periodic duty correction operations where the duty correction circuit continuously monitors and adjusts the internal clock signal duty cycle based on the external clock signal. This periodic adjustment ensures duty cycle accuracy is maintained even during high-frequency data transmission operations.
Data Source
AI summary
Provided is a nonvolatile memory including a clock pin configured to receive an external clock signal during a duty correction circuit training period; a plurality of memory chips configured to perform a duty correction operation on an internal clock signal based on the external clock signal, the plurality of memory chips configured to perform the duty correction operation in parallel during the training period; and an input/output pin commonly connected to the plurality of memory chips, wherein each of the plurality of memory chips includes: a duty correction circuit (DCC) configured to perform the duty correction operation on the internal clock signal; and an output buffer connected between an output terminal of the DCC and the input/output pin.