Parallel E-Fuse Adaptive Current Balancing

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Solution Overview

Problem

Current parallel E-Fuses in SSDs face issues with current imbalance, leading to uneven power distribution and increased thermal shutdown, which is addressed by traditional methods that reduce efficiency and increase power consumption.

Innovation Solution

A parallel e-fuse device with adaptive current balancing, where the first and second e-fuses activate or deactivate current balancing based on operation modes such as soft-start and clamp modes, minimizing power loss by selectively applying current balancing only when necessary.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If current balancing is continuously activated in parallel E-Fuses, then current distribution is improved, but power consumption increases and efficiency decreases

Engineering Contradiction:
Improvecurrent distribution stabilityVSAvoidpower consumption
Core Design Contradiction:
ReliabilityVSUse of energy by moving object

Solution Approach 1:

The patent implements dynamic current balancing by enabling the balancing function only during specific operation modes (soft-start and clamp modes) rather than continuously. The balancing operation is controlled by a mode signal that activates or deactivates the balancing amplifiers based on the operational state, thereby reducing unnecessary power consumption while maintaining current distribution stability when needed.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The patent changes the operational parameter of the current balancing function from a static continuous state to a dynamic conditional state. By monitoring operation modes and adjusting the activation state of balancing amplifiers accordingly, the system optimizes the balance between current distribution reliability and power consumption efficiency.

Inventive Principle:
Principle #35Parameter changes

2Reliability

If current balancing is activated to prevent thermal shutdown, then system stability is improved, but overall efficiency decreases due to increased power consumption

Engineering Contradiction:
Improvesystem stabilityVSAvoidpower loss
Core Design Contradiction:
ReliabilityVSLoss of energy

Solution Approach 1:

The patent dynamically controls the current balancing function based on operational requirements. During soft-start and clamp modes where current imbalance poses a risk, the balancing amplifiers are activated to maintain system stability. During normal operation modes, the balancing function is deactivated to minimize energy loss, thereby optimizing the trade-off between system stability and energy efficiency.

Inventive Principle:
Principle #15Dynamics

3Power

If E-Fuses operate in parallel to increase power capacity, then power delivery is improved, but current imbalance causes uneven power distribution and thermal issues

Engineering Contradiction:
Improvepower delivery capacityVSAvoidcurrent balance
Core Design Contradiction:
PowerVSReliability

Solution Approach 1:

The patent employs feedback mechanisms through balance amplifiers that monitor current distribution among parallel E-Fuses. The amplifiers compare current levels and adjust gate voltages of power transistors to equalize current flow, ensuring reliable operation of parallel E-Fuse configurations while maintaining the enhanced power delivery capacity.

Inventive Principle:
Principle #23Feedback

Solution Approach 2:

The patent introduces balance amplifiers as intermediary control elements between the parallel E-Fuses. These amplifiers act as mediators that sense current imbalances and generate corrective control signals to adjust power transistor gating, thereby maintaining current balance without directly altering the E-Fuse structure or operation.

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS20240347114A1Serial interface receiver and an offset calibration method thereof
Publication Date: 2024.10.17 SAMSUNG ELECTRONICS CO LTD
  • US20240347114A1 patent drawing
  • US20240347114A1 patent drawing
  • US20240347114A1 patent drawing

AI summary

A parallel e-fuse device including: a first e-fuse to receive an input voltage and transfer a first fuse current to an output terminal; and a second e-fuse to receive the input voltage and transfer a second fuse current to the output terminal, the first e-fuse includes: a power transistor to control the first fuse current according to a gate voltage; a clamp amplifier to provide a charging current to charge a gate of the power transistor, the charging current being obtained by monitoring a feedback voltage; a balance amplifier to provide a first sinking current to discharge the gate of the power transistor, the first sinking current being obtained by comparing a current sensing signal with a current monitoring signal, wherein the clamp amplifier generates the charging current according to a differential voltage between the feedback voltage and a reference voltage.