Parallel ECC Circuits for Masked Write Data Correction
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Solution Overview
Problem
In integrated circuits, the implementation of error correction codes (ECC) with a data mask option poses challenges due to the dependency of parity codes on both new and old data, leading to inefficiencies in processing time and overhead, especially when sequential ECC operations are required, which can be unacceptable in certain instances.
Innovation Solution
The use of parallel ECC circuits that operate independently to correct data errors in old data words and generate new parity codes, allowing for simultaneous correction and encoding, thereby reducing processing time and overhead during write operations with a data mask.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If sequential ECC decode and encode operations are used during write operations with data mask, then data errors can be corrected, but processing time is excessively long and productivity is reduced
Solution Approach 1:
The patent divides the ECC correction system into multiple independent parallel circuits (first ECC circuit, second ECC circuit, third ECC circuit) that operate simultaneously on different portions of the data word. Each circuit handles a segment of the data independently, allowing concurrent error correction across multiple segments rather than sequential processing of the entire data word.
Solution Approach 2:
The patent transitions from a single-threaded sequential ECC processing approach to a multi-threaded parallel processing architecture. By introducing multiple ECC circuits that operate in parallel dimensions simultaneously, the system achieves faster overall processing while maintaining comprehensive error correction coverage across all data portions.
2Reliability
If sequential ECC operations are performed, then data integrity is maintained, but processing overhead and time consumption increase
Solution Approach 1:
The patent performs preliminary error correction on segmented data portions through multiple parallel ECC circuits before the final merge operation. By pre-correcting errors in each segment concurrently, the system avoids the need for time-consuming sequential correction after merging, thus reducing overall processing time while ensuring data integrity.
Solution Approach 2:
The patent maintains continuous error correction capability across all data segments through parallel circuits that operate simultaneously without idle waiting periods. This continuous parallel processing eliminates the stop-start nature of sequential operations, reducing total processing time while maintaining uninterrupted data integrity protection.
3Adaptability or versatility
If multiple separate parity codes are used for each data portion, then error correction flexibility is improved, but device complexity and overhead increase
Solution Approach 1:
The patent divides the data word into multiple portions, each handled by a dedicated ECC circuit that generates and processes parity codes for its specific segment. This segmentation provides flexibility in correcting errors in different data portions independently while using standardized ECC circuit designs, balancing adaptability with manageable complexity.
Solution Approach 2:
The patent employs multiple ECC circuits that use the same error correction algorithm and parity code structure across different data segments. This universal approach provides flexible error correction capability for each segment while avoiding the complexity of implementing different correction methods, achieving versatility through repetition of a proven design pattern.
Data Source
AI summary
One example apparatus includes a first circuit configured to receive first and second data words, to correct one or more errors in the first data word, to merge the corrected first data word and the second data word responsive to a control signal to generate a final merged data word, and to provide the final merged data word to a write circuit. The apparatus also includes a second circuit configured to also receive the first and second data words, to preliminarily merge the first and second data words responsive to the control signal to generate an initial merged data word, to generate an initial parity code for the initial merged data word, to correct the initial parity code, and to provide the corrected parity code to the write circuit.