Parallel ECC Decoding for NAND Codewords Sharing Data Blocks

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Solution Overview

Problem

In NAND flash storage, error correcting code (ECC) decoders face data dependency issues when decoding constituent codewords that share common data blocks, leading to unpredictable hardware behavior and increased complexity, especially with multiple parallel decoders.

Innovation Solution

A decoder architecture that performs coarse and fine decoding, where coarse decoding involves parallel decoding of multiple codewords to determine error information and correct errors in one codeword, while fine decoding corrects errors sequentially, preventing updates in codewords sharing common blocks if the common block is already corrected.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If multiple decoders operate in parallel to decode codewords sharing common data blocks, then decoding throughput is improved, but data dependency causes unpredictable hardware behavior and increased complexity

Engineering Contradiction:
Improvedecoding throughputVSAvoiddecoder architecture complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The decoding process is segmented into two distinct phases: coarse decoding that processes all codewords in parallel to identify error locations, and fine decoding that sequentially corrects errors in each codeword. This segmentation allows parallel processing benefits while avoiding data dependency conflicts in the correction stage.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The coarse decoding phase performs preliminary error detection and location identification for all codewords before any correction takes place. By determining all error locations upfront in parallel, the system eliminates data dependencies during the subsequent fine decoding correction phase.

Inventive Principle:
Principle #10Preliminary action

2Loss of time

If parallel decoding is used to meet throughput requirements, then read latency is reduced, but data dependency among constituent codes becomes severe

Engineering Contradiction:
Improveread latencyVSAvoiddecoding reliability
Core Design Contradiction:
Loss of timeVSReliability

Solution Approach 1:

The decoding is divided into coarse decoding (parallel error detection) and fine decoding (sequential correction). This segmentation maintains high throughput by parallelizing the time-critical error detection while ensuring reliability through sequential correction that avoids data dependency issues.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The coarse decoding phase acts as an intermediary that processes all codewords in parallel to generate error location information, which then mediates the subsequent fine decoding correction process. This intermediary step separates the parallel processing from the correction operations, eliminating data dependency conflicts.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Productivity

If constituent decoders run in parallel with overlap in decoding time, then throughput is improved, but clash in updating errors in shared data bits occurs

Engineering Contradiction:
Improvedecoding throughputVSAvoiderror update consistency
Core Design Contradiction:
ProductivityVSEase of operation

Solution Approach 1:

The decoding process is segmented into error detection (coarse decoding) and error correction (fine decoding) phases. During coarse decoding, multiple decoders operate in parallel to identify errors without updating data. During fine decoding, corrections are applied sequentially to each codeword, preventing clashes in updating shared data bits.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

All error locations in shared data blocks are preliminarily identified during the coarse decoding phase before any correction operations begin. This preliminary error detection ensures that when fine decoding corrections are applied sequentially, there are no conflicts from simultaneous updates to the same data bits.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS10484020B2System and method for parallel decoding of codewords sharing common data
Publication Date: 2019.11.19 SK HYNIX INC
  • US10484020B2 patent drawing
  • US10484020B2 patent drawing
  • US10484020B2 patent drawing

AI summary

A memory device can include a memory array, a processor coupled to the memory array, and a decoding apparatus. The decoding apparatus is configured to perform parallel decoding of codewords. Each of the codewords has a plurality of data blocks, and each data block having a number of data bits. The decoding apparatus is configured to decode, in parallel, a first codeword with one or more other codewords to determine error information associated with each codeword. For errors in a common data block shared between two codewords being decoded in parallel, the error information includes a data block identifier and associated error bit patterns. Further, the decoding apparatus is configured to update the codewords based on the error information.