Parallel eFuse Memory Cell Design for Yield Improvement
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Solution Overview
Problem
The existing eFuse technology faces challenges in ensuring a high yield rate due to variability in fusing currents of electric fuses, leading to defective eFuse memory cells and arrays, as the fusing current is influenced by environmental parameters like melting point, room temperature, and quality of the fuse.
Innovation Solution
The introduction of an eFuse memory cell design featuring a first electric fuse and one or more second electric fuses connected in parallel, where the second fuses are connected in parallel with the first fuse, allowing for programming opportunities even if the first fuse fails, thereby improving the yield rate of the eFuse memory array.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a single electric fuse is used in the eFuse memory cell, then the device complexity is low, but the yield rate is poor due to fusing current variability
Solution Approach 1:
The single electric fuse is segmented into multiple parallel fuses (first electric fuse and second electric fuse). Each fuse can independently perform the programming function, so if one fuse fails to program due to current variability, the other fuse can still complete the programming, thereby improving the yield rate while maintaining relatively simple device structure
Solution Approach 2:
The patent introduces a redundant second electric fuse that serves as a backup before the actual programming operation. This beforehand cushioning ensures that even if the first fuse fails during programming due to current variability, the second fuse is already in place to compensate, thus improving reliability without significantly increasing complexity
2Productivity
If multiple parallel fuses are used to improve programming success rate, then the yield rate is improved, but the device complexity increases
Solution Approach 1:
The programming function is segmented across multiple parallel fuses rather than relying on a single fuse. This segmentation allows the system to achieve higher programming success rates because each fuse operates independently and can compensate for failures in others, while the overall device complexity remains manageable through the simple parallel configuration
Solution Approach 2:
The patent changes the parameter of fuse quantity from one to multiple, which directly improves the programming success rate by providing statistical redundancy against current variability. The complexity increase is minimized by maintaining the same basic fuse structure and using simple parallel connection rather than complex control circuits
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design ensures each eFuse memory cell has a chance to be programmed at least twice, significantly enhancing the yield rate of both individual cells and the eFuse memory array by providing redundancy through parallel-connected fuses.
Implementation Method 1
it is controlled whether the electric fuse is fused through a current in a control circuit
Implementation Method 2
the fusing current is influenced by environmental parameters like melting point
Data Source
AI summary
An eFuse memory cell, an eFuse memory array and a using method thereof, and an eFuse system are provided. In one form, an eFuse memory cell includes: a programming transistor, where a source of the programming transistor is grounded; a first electric fuse having a first terminal and a second terminal opposite to the first terminal, where the first terminal is connected to a drain of the programming transistor; one or more second electric fuses connected in parallel to each other, where each of the second electric fuses is connected in parallel with the first electric fuse, the second electric fuse has a third terminal and a fourth terminal opposite to the third terminal, and the third terminal is connected to the drain of the programming transistor; a word line connected to a gate of the programming transistor; a first programming bit line connected to the second terminal of the first electric fuse; and one or more second programming bit lines in a one-to-one correspondence with the second electric fuses, the second programming bit line being connected to the fourth terminal of the corresponding second electric fuse. The eFuse memory cell provided in the present disclosure has an opportunity to be programmed at least twice, thereby improving a yield rate of the eFuse memory array.