Parallel-Electrode Chip Capacitor for Low Loop Inductance
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing component-embedded substrates with chip capacitors suffer from high loop inductance and poor high-frequency noise absorption due to the perpendicular stacking of internal electrodes, leading to inadequate high-frequency responsiveness and noise absorption performance.
Innovation Solution
The substrate incorporates a chip capacitor with internal electrodes stacked parallel to the principal surfaces, featuring terminal electrodes that connect via a dielectric layer, reducing loop inductance and enhancing high-frequency responsiveness and noise absorption by minimizing inductance and resistance in the current path.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If internal electrodes of the capacitor are stacked in a direction perpendicular to the substrate, then the capacitor can be connected to power supply and IC chip through via holes, but the loop inductance of the route passing through the capacitor is increased
Solution Approach 1:
The patent inverts the conventional perpendicular stacking direction of internal electrodes to a parallel direction relative to the substrate surface. This inversion fundamentally changes the current path geometry, reducing loop inductance and improving high-frequency responsiveness while maintaining manufacturing feasibility through modified electrode connections.
Solution Approach 2:
The patent transitions from one-dimensional perpendicular stacking to two-dimensional parallel arrangement of internal electrodes. This dimensional change allows the current to flow through a shorter, more direct path within the capacitor structure, significantly reducing loop inductance while maintaining electrical connectivity.
2Device complexity
If high-frequency electric current flows in the external electrode first and subsequently in the capacitor, then the connection is simplified, but the high-frequency electric current is negligibly absorbed by the capacitor
Solution Approach 1:
The patent applies local quality by creating different functional zones within the capacitor structure. The parallel-stacked internal electrodes provide localized high-frequency current absorption paths with low inductance, while external electrodes maintain simplified connections. This spatial differentiation of functions simultaneously achieves simple connectivity and effective noise absorption.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration significantly improves high-frequency responsiveness and noise absorption performance by reducing inductance and impedance, allowing for more efficient high-frequency current flow and noise absorption.
Implementation Method 1
Capacitance is provided by at least one pair of the terminal electrodes in the first terminal electrode group via the dielectric layer, and capacitance is provided by at least one pair of the terminal electrodes in the second terminal electrode group via the dielectric layer
Implementation Method 2
the ceramic laminate body includes a dielectric layer and a plurality of internal electrodes stacked along the dielectric layer
Data Source
AI summary
A component-embedded substrate includes a chip capacitor. The chip capacitor includes a ceramic laminate body and a plurality of terminal electrodes. The component-embedded substrate has a first principal surface and a second principal surface. At least two of the plurality of terminal electrodes are connected to the first principal surface and define a first terminal electrode group, and at least two of the plurality of terminal electrodes are connected to the second principal surface and define a second terminal electrode group. One terminal electrode in the first terminal electrode group is electrically connected to one terminal electrode in the second terminal electrode group via the internal electrodes, and capacitance is provided by a pair of the terminal electrodes in the first terminal electrode group via the dielectric layer, and capacitance is provided by a pair of the terminal electrodes in the second terminal electrode group via the dielectric layer. A direction in which the internal electrodes are stacked is parallel or substantially parallel to the two principal surfaces.