Parallel Encoder Delays for Low Error Floor Decoding
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Solution Overview
Problem
Existing error correction codes in information transmission and recording face an 'error floor' phenomenon, where bit error ratio does not decrease quickly with increasing signal-to-noise ratio, and existing solutions either result in rate loss, significant decoding complexity, or require complex techniques to identify and correct pathological patterns.
Innovation Solution
A novel encoder architecture that uses multiple component encoders with interconnections to generate and forward reduced local code words with varying delays, allowing for a lower-bound on the minimum Hamming distance and eliminating the error floor while maintaining low constraint length and complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If an outer algebraic code is used to remove the error floor, then the error floor is reduced, but rate loss occurs and decoding complexity increases
Solution Approach 1:
The encoder segments the information flow into multiple parallel component encoders (first, second, third component encoders) that process different portions of the data simultaneously. This segmentation allows the system to achieve error floor reduction through the structured parallel architecture without requiring complex outer algebraic codes, as each component encoder contributes to the overall error correction capability through its specific interconnection pattern and delay elements.
Solution Approach 2:
The invention introduces a temporal dimension through delay elements (D1, D2, D3, D4) that store and retransmit encoded bits at different time instances. This transforms the error correction mechanism from a spatial/algebraic approach to a temporal approach, where the same information bits are processed multiple times at different delays, enabling error floor reduction without increasing algebraic complexity.
2Reliability
If codes with large Hamming distance are used to eliminate error floor, then error floor is reduced, but constraint length and latency increase
Solution Approach 1:
The invention merges multiple component encoders with identical or similar structures into a unified encoding system. By combining the outputs of multiple component encoders with specific interconnections and delay elements, the system achieves an effective large minimum Hamming distance without requiring any single component encoder to have excessively long constraint length, thus reducing latency while maintaining reliability.
Solution Approach 2:
Delay elements (D1, D2, D3, D4) act as intermediaries that buffer and retransmit encoded bits between component encoders. These intermediaries allow the system to achieve the benefits of large Hamming distance through multiple processing passes without requiring the information to traverse excessively long constraint lengths, thereby reducing latency while maintaining error correction capability.
3Reliability
If Braided Block Codes are used to achieve excellent error correcting performance, then error correction is improved, but constraint length and complexity grow rapidly
Solution Approach 1:
Each component encoder in the invention has a simple, localized structure with a small constraint length, processing only a portion of the information bits at a time. This local quality approach allows the overall system to achieve excellent error correction performance through the coordinated interaction of multiple simple components, rather than requiring a single complex encoder with large constraint length.
Solution Approach 2:
The encoding function is segmented across multiple component encoders, each handling a specific portion of the data with simple local logic. This segmentation breaks down the complex error correction task into manageable pieces that can be processed in parallel, reducing the constraint length and complexity of individual components while maintaining overall error correction performance through their interconnections.
Data Source
AI summary
An encoder encodes digital data, said encoder includes one or more component encoders, one or more interconnections between component encoders, one or more inputs and one or more outputs. The encoder is configured to carry out the following steps: combining internal input bits received via an interconnection and external input bits received via a corresponding input, to assemble a local information word, encoding the local information word such as to generate a local code word, outputting a reduced local code word and handling the same reduced local code word over to the interconnect for forwarding the same reduced local code word to another component encoder or to itself, wherein the encoder is configured to forward on each interconnect the bits of the reduced local code in parallel but with delays that are mutually different for at least a subset of the reduced local code word bits.