Parallel Encoder Synchronization for High-Resolution Video
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional encoding and decoding systems for high-resolution moving-picture signals, such as HDTV and UDTV, face challenges in achieving synchronization of display time due to clock deviations among multiple encoders and decoders, leading to incorrect display of high-resolution signals.
Innovation Solution
The system divides high-resolution image data into multiple low-resolution signals, which are encoded and decoded using low-performance encoders and decoders, with a method to synchronize display time by calculating and adjusting the encoding and decoding delays, ensuring all decoders output data at the same time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If multiple encoders and decoders are used to process high-resolution moving-picture signals, then the processing capability and resolution are improved, but synchronization of display time cannot be achieved due to clock deviations between devices
Solution Approach 1:
The invention applies preliminary action by calculating the display time offset between multiple encoders and decoders in advance, before actual encoding and decoding operations. The offset information is embedded in the encoded data, allowing decoders to pre-adjust their timing to achieve synchronized display without requiring complex real-time clock synchronization mechanisms.
2Manufacturing precision
If high-performance encoding and decoding systems are used to handle high-resolution moving-picture signals, then the quality and resolution are improved, but the system cost and hardware requirements increase significantly
Solution Approach 1:
The invention applies segmentation by dividing the high-resolution moving-picture signal into multiple low-resolution signals that can be processed by ordinary, low-performance encoders and decoders. The division is based on display area segmentation, where different portions of the high-resolution image are assigned to different encoding/decoding units. This allows the use of multiple simple devices instead of one complex high-performance system, significantly reducing hardware costs while maintaining overall image quality.
3Ease of manufacture
If high-resolution moving-picture signals are divided into multiple low-resolution signals and processed by low-performance encoders, then the hardware requirements are reduced, but correct display cannot be achieved due to timing deviations
Solution Approach 1:
The invention applies feedback by calculating and determining the display time offset between multiple encoders and decoders, then using this offset information to adjust the timing of decoded signals. The offset calculation considers the specific characteristics of each encoder and decoder, and this feedback mechanism ensures that even though different devices are used, the final displayed images are synchronized and correctly timed, maintaining display reliability.
Data Source
Figure 1
Figure 2
Figure 3~4
AI summary
An encoding system that encodes image data of one picture by a plurality of encoders (301, ... 30n) so that each piece of the encoded data encoded by the encoders becomes a slice of one picture, the encoding system comprising a distributing unit (52) that obtains a value of a predetermined STC counter as a reference time so that the value of the predetermined STC counter synchronizes with a video vertical-synchronizing signal, and distributes a value obtained by adding one-cycle value of the video vertical-synchronizing signal to the obtained STC counter value to each of the encoders, the reference time being a reference at the time of encoding a sliced portion of the image data in each of the encoders, wherein each of the encoders includes a setting unit (31) that holds the value distributed by the distributing unit in a register included in the encoder, upon reception of the distributed value, and sets the value held in the register as the value of the STC counter included in the encoder so that the value synchronizes with the video vertical-synchronizing signal first received after holding the value in the register.