Parallel Multi-Dimensional Encoding for Low Error-Floor NAND Flash

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Solution Overview

Problem

Existing multi-dimensional encoding methods in NAND flash memory systems face challenges in achieving a low error-floor and efficient redundancy protection, particularly in serial concatenation and 3D applications where redundancy is not effectively integrated into the encoding process.

Innovation Solution

A parallel multi-dimensional encoding method is introduced, where multiple versions of a group of bits are encoded in parallel, with each version responsive to the redundancy results of the other, using a primitive element matrix and syndrome vector to compute redundancy bits that represent the output of both sets of bits, allowing for simultaneous encoding of redundancy across dimensions.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of manufacture

If serial concatenation encoding is used, then the encoding process is simpler to implement, but the error-floor is higher and redundancy protection is less effective

Engineering Contradiction:
Improveencoding implementation simplicityVSAvoiderror-floor
Core Design Contradiction:
Ease of manufactureVSReliability

Solution Approach 1:

The patent merges multiple encoding dimensions (first dimension encoding and second dimension encoding) into a parallel processing framework. Instead of sequentially concatenating codes, the system simultaneously encodes data bits and redundancy bits across multiple dimensions, with each dimension's encoding being responsive to the other. This integration reduces the error-floor by ensuring comprehensive redundancy protection while maintaining implementation feasibility through structured parallel processing.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The patent transitions from one-dimensional serial concatenation to multi-dimensional parallel encoding. By introducing a second encoding dimension that operates in parallel with the first dimension, the system achieves better error correction performance and lower error-floor. The second dimension encodes redundancy bits that are responsive to the first dimension's encoding results, creating a more robust error protection mechanism without significantly increasing implementation complexity.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Device complexity

If 3D applications with separate redundancy encoding are used, then the encoding structure is more organized, but redundancy is not effectively integrated into the encoding process

Engineering Contradiction:
Improveencoding structure organizationVSAvoidredundancy protection effectiveness
Core Design Contradiction:
Device complexityVSReliability

Solution Approach 1:

The patent implements feedback mechanisms where the encoding of the second set of bits is responsive to the first redundancy result of the encoding of the first set of bits, and the encoding of the first set of bits is responsive to the second redundancy result of the encoding of the second set of bits. This cross-dimensional feedback ensures that redundancy bits are effectively integrated into the encoding process, with each dimension's encoding informing and improving the other, thereby enhancing overall redundancy protection effectiveness while maintaining organized encoding structure.

Inventive Principle:
Principle #23Feedback

Solution Approach 2:

The patent performs preliminary encoding actions by computing redundancy bits for multiple dimensions in parallel before final codeword assembly. The system calculates redundancy results for both first and second dimension encodings simultaneously, using primitive element matrices and syndrome vectors to efficiently determine redundancy bits. This preliminary parallel computation ensures that redundancy is effectively integrated into the encoding process from the outset, rather than being added sequentially after the fact.

Inventive Principle:
Principle #10Preliminary action

3Reliability

If parallel multi-dimensional encoding is implemented, then redundancy protection is more effective and error-floor is reduced, but the encoding complexity increases

Engineering Contradiction:
Improveerror-floorVSAvoidencoding process complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent segments the encoding process into distinct but parallel dimension-specific encoding operations. Each dimension has its own encoding logic and redundancy calculation, allowing the complex multi-dimensional encoding to be broken down into manageable segments. The first dimension encoding and second dimension encoding are treated as separate segments that can be computed in parallel, reducing the perceived complexity while maintaining the benefits of multi-dimensional redundancy protection and low error-floor.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent utilizes parameter changes through the use of primitive element matrices and syndrome vectors to efficiently manage the complexity of parallel multi-dimensional encoding. By representing encoding operations in terms of mathematical parameters (primitive elements, matrices, and vectors), the system can perform complex redundancy calculations through systematic parameter manipulation rather than ad-hoc logic. This parameter-based approach reduces encoding process complexity by providing a unified mathematical framework for handling multiple dimensions simultaneously.

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS9407291B1Parallel encoding method and system
Publication Date: 2016.08.02 AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE LTD
  • US9407291B1 patent drawing
  • US9407291B1 patent drawing
  • US9407291B1 patent drawing

AI summary

A method for parallel multi-dimensional encoding, the method may include receiving or generating a first version of a group of bits and a second version of the group of bits, wherein the first and second versions differ from each other by an arrangement of bits of the data unit; selecting a first set of bits of the first version and a second set of bits of the second version; encoding, in parallel, the first set of bits and the second set of bits; wherein the encoding of the second set of bits is responsive to the second set of bits and a first redundancy result of the encoding of the first set of bits; and wherein the encoding of the first set of bits is responsive to the first set of bits and to a second redundancy result of the encoding of the second set of bits.