Parallel Encryption Engines for SSD Data Throughput
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Solution Overview
Problem
Existing encryption methods, such as AES in feedback modes like CBC, introduce latencies in pipelined data processing due to the need for feedback loops, which can hinder high-speed data processing in applications like solid state drives (SSDs) with high throughput rates.
Innovation Solution
Implementing parallel encryption engines arranged in a round robin configuration to distribute and process data groups across multiple AES engines, allowing for continuous encryption/decryption at high speeds without the latency introduced by feedback loops, using an input logic circuit, output logic circuit, and multiple encryption/decryption circuits capable of processing data at rates matching or exceeding the interface throughput.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If feedback modes like CBC are used for AES encryption, then security is improved, but processing speed deteriorates due to latencies introduced by feedback loops
Solution Approach 1:
The patent divides the data stream into multiple independent data groups and distributes them to multiple AES engines operating in parallel. Each engine processes its assigned data group independently without requiring feedback from previous groups, eliminating the latency bottleneck while maintaining security through parallel cryptographic processing
Solution Approach 2:
The patent transitions from sequential single-engine processing to multi-dimensional parallel processing by deploying multiple AES engines simultaneously. This dimensional shift from one-dimensional sequential execution to two-dimensional parallel execution allows multiple encryption operations to occur concurrently, resolving the speed-security tradeoff
2Device complexity
If a single AES engine processes data sequentially, then device complexity is reduced, but throughput rate deteriorates and cannot meet high-speed interface requirements
Solution Approach 1:
The patent combines multiple AES engines into a unified parallel processing system where each engine handles a portion of the data stream. The input logic circuit and output logic circuit merge the coordinated output from multiple engines to produce the final encrypted/decrypted data stream, achieving high throughput while distributing complexity across multiple specialized units
3Productivity
If parallel encryption engines are implemented, then data processing speed is improved, but device complexity increases due to multiple circuits and logic circuits
Solution Approach 1:
The patent designs each AES engine as a universal cryptographic unit capable of performing both encryption and decryption operations. The engines share common control logic and can process different data groups through the same cryptographic algorithm, reducing overall system complexity despite having multiple processing units
Solution Approach 2:
The input logic circuit and output logic circuit serve as intermediary components that coordinate data distribution to multiple AES engines and aggregate their outputs. These mediators simplify the interface between the parallel engines and the external data stream, managing the complexity of parallel coordination without requiring complex inter-engine communication
Data Source
AI summary
The present disclosure includes methods and devices for parallel encryption/decryption. In one or more embodiments, an encryption/decryption device includes an input logic circuit, an output logic circuit, and a number of encryption/decryption circuits arranged in parallel between the input logic circuit and the output logic circuit. For example, each encryption/decryption circuit can be capable of processing data at an encryption/decryption rate, and the number of encryption/decryption circuits can be equal to or greater than an interface throughput rate divided by the encryption/decryption rate.