Context-Adaptive Video Processor Parallel Entropy Coding

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Solution Overview

Problem

Conventional H.264 video processors face bottlenecks in encoding and decoding due to the complexity of CABAC and CAVLC processes, which limits the maximum bit rate and performance, especially in parallelizing operations across symbols.

Innovation Solution

Implementing two independent entropy coder circuits (CAVLC/CABAC) decoupled from the transform stage, allowing them to operate simultaneously on different pictures or frames, and storing coefficients in memory to balance load and improve performance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Loss of information

If CABAC encoding/decoding is used to achieve more efficient compression, then compression efficiency is improved, but processing speed deteriorates due to complexity requiring more than 2 clock cycles per symbol

Engineering Contradiction:
Improvecompression efficiencyVSAvoidprocessing speed
Core Design Contradiction:
Loss of informationVSProductivity

Solution Approach 1:

The patent divides the single entropy coding function into two separate entropy coder circuits, each handling different symbol types or processing stages. This segmentation allows parallel processing of different coefficient groups simultaneously, maintaining CABAC's compression efficiency while doubling the throughput by eliminating the sequential bottleneck

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent transitions from single-threaded sequential entropy coding to multi-threaded parallel entropy coding by introducing a second coder circuit. This dimensional change from 1D sequential processing to 2D parallel processing space enables simultaneous operation of multiple coding streams, resolving the speed-efficiency tradeoff

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Productivity

If the entropy coder is connected directly to the transform function circuit to enable parallel pixel processing, then transform performance is improved, but the entropy coder becomes a bottleneck due to inability to parallelize operations across symbols

Engineering Contradiction:
Improvetransform processing performanceVSAvoidsystem bottleneck
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent segments the entropy coding workload into two independent coder circuits that can process different symbol streams in parallel. This segmentation removes the single-point bottleneck while maintaining the direct connection architecture between transform and entropy coding stages

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent prepares multiple entropy coder circuits in advance, each ready to process different symbol types or processing lanes simultaneously. This preliminary preparation of parallel coding resources eliminates the bottleneck effect during actual video processing operations

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS8391367B1High performance context-adaptive video processor
Publication Date: 2013.03.05 AMBARELLA INT LP
  • US8391367B1 patent drawing
  • US8391367B1 patent drawing
  • US8391367B1 patent drawing

AI summary

An apparatus comprising a transform circuit, a first coder circuit, a second coder circuit, and a memory circuit. The transform circuit may be configured to generate (i) one or more first coefficients in response to a sample signal when in a first mode and (ii) the sample signal in response to the first coefficients when in a second mode. The first coder circuit may be configured to generate (i) a first bitstream signal in response to one or more second coefficients when in the first mode and (ii) the second coefficients in response to the first bitstream signal when in the second mode. The second coder circuit may be configured to generate (i) a second bitstream signal in response to one or more third coefficients when in the first mode and (ii) the third coefficients in response to the second bitstream signal when in the second mode. The memory circuit may be configured to store the first coefficients, the second coefficients, and the third coefficients. The memory may be configured to allow the transform circuit, the first coder circuit, and the second coder circuit to operate independently.