Parallel Hardware Entropy Encoder for Full-Rate Data Compression
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Solution Overview
Problem
Conventional software implementations of data compression encoders are limited by high power consumption, size, weight, and slow processing speeds, which are unsuitable for applications with stringent size, weight, and power constraints, such as space or airborne systems, and fail to maintain output rates matching incoming data rates.
Innovation Solution
A novel hardware-based entropy encoder architecture that splits incoming data streams into fundamental sequence and k-split streams, processed in parallel, using a fundamental sequence intermediate format and zero-word expander to achieve full-speed input and output rates, with internal rate buffering to maintain synchronization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If conventional software implementations of data compression encoders are used, then encoding functionality is provided, but power consumption is high, size and weight are large, and processing speed is slow
Solution Approach 1:
The patent replaces software-based encoding with a hardware-based encoder circuit that implements Rice encoding algorithms. This substitution of mechanical/electronic system for software system achieves faster processing speeds and lower power consumption by utilizing dedicated hardware logic instead of general-purpose processor execution, directly resolving the contradiction between speed and power consumption.
Solution Approach 2:
The encoder circuit is divided into multiple functional blocks including a first circuit for fundamental sequence encoding, a second circuit for k-split data stream generation, and a third circuit for combining results. This segmentation allows parallel processing of different aspects of the encoding algorithm, significantly improving processing speed while maintaining efficient power utilization through specialized hardware paths.
2Weight of stationary object
If conventional software implementations are used, then encoding is performed, but size and weight are large
Solution Approach 1:
The patent replaces software implementations with a dedicated hardware encoder circuit, dramatically reducing size and weight by eliminating the need for general-purpose processors and software storage. The hardware circuit provides the same encoding functionality in a compact form factor suitable for space and airborne applications, while maintaining full processing capability.
Solution Approach 2:
The encoder circuit is designed to handle multiple encoding operations and data formats through configurable parameters and modular architecture. This universality allows a single hardware device to perform various compression tasks, reducing the need for multiple specialized components and thereby minimizing overall system size and weight.
3Speed
If hardware-based encoders are used, then processing speed increases and size/weight/power decrease, but conventional hardware encoder architectures are either too large or too slow to match input data rates
Solution Approach 1:
The encoder is segmented into specialized circuits that process different portions of the encoding algorithm in parallel. The first circuit handles fundamental sequence encoding, the second circuit processes k-split operations, and the third circuit combines results. This segmentation enables the output rate to match input data rates while keeping each individual circuit block manageable in complexity.
Solution Approach 2:
The hardware encoder performs preliminary processing steps in parallel pipelines, preparing data for final encoding before output. This preliminary action allows the system to maintain full-speed input and output rates by pre-processing data through multiple stages simultaneously, avoiding bottlenecks that would increase overall system complexity.
Data Source
AI summary
A data encoder. The novel encoder includes a first circuit for generating a fundamental sequence coded data stream from an incoming input data stream, a second circuit for generating a k-split data stream from the incoming data stream, and a third circuit for combining the fundamental sequence coded data stream and k-split data stream to form a final encoded output. The first circuit includes a circuit for converting the incoming input data stream into a novel intermediate format comprising a set bit word and a zero word count, and a zero-word expander for converting the intermediate format to the fundamental sequence coded data stream. The first circuit may also include a register adapted to store the intermediate format to provide rate buffering.